A tri-level 50MS/s 10-bit capacitive-DAC for Bluetooth applications

Abstract

This document summarizes, for the university design contest, a chip design of a low power dissipation and small die area 10-bit capacitive digital-to-analog converter (DAC) in a 0.18 µm CMOS process. Power dissipation of this chip is 350 µW including the output buffers. The die area is 0.081mm 2 .