To make graphene technologically viable, the transfer of graphene films to substrates appropriate for specific applications is required. We demonstrate the dry transfer of epitaxial graphene (EG) from the C-face of 4H-SiC onto SiO(2), GaN and Al(2)O(3) substrates using a thermal release tape. Subsequent Hall effect measurements illustrated that minimal degradation in the carrier mobility was induced following the transfer process in lithographically patterned devices. Correspondingly, a large drop in the carrier concentration was observed following the transfer process, supporting the notion that a gradient in the carrier density is present in C-face EG, with lower values being observed in layers further removed from the SiC interface. X-ray photoemission spectra collected from EG films attached to the transfer tape revealed the presence of atomic Si within the EG layers, which may indicate the identity of the unknown intrinsic dopant in EG. Finally, this transfer process is shown to enable EG films amenable for use in device fabrication on arbitrary substrates and films that are deemed most beneficial to carrier transport, as flexible electronic devices or optically transparent contacts.

Because of its ultra-wide bandgap, high breakdown electric field, and large-area affordable substrates grown from the melt, β-Ga2O3 has attracted great attention recently for potential applications of power electronics. However, its thermal conductivity is significantly lower than those of other wide bandgap semiconductors, such as AlN, SiC, GaN, and diamond. To ensure reliable operation with minimal self-heating at high power, proper thermal management is even more essential for Ga2O3 devices. Similarly to the past approaches aiming to alleviate selfheating in GaN high electron mobility transistors (HEMTs), a possible solution has been to integrate thin Ga2O3 membranes with diamond to fabricate Ga2O3-on-diamond lateral metalsemiconductor field-effect transistor (MESFET) or metal-oxide-semiconductor field-effect transistor (MOSFET) devices by taking advantage of the ultra-high thermal conductivity of diamond. Even though the thermal boundary conductance (TBC) between wide bandgap semiconductor devices such as GaN HEMTs and a diamond substrate is of primary importance for heat dissipation in these devices, fundamental understanding of the Ga2O3/diamond thermal interface is still missing. In this work, we study the thermal transport across the interfaces of Ga2O3 exfoliated onto a single crystal diamond. The Van der Waals bonded Ga2O3-diamond TBC is measured to be 17 -1.7/+2.0 MW/m 2 -K, which is comparable to the TBC of several physical-vapor-deposited metals on diamond. A Landauer approach is used to help understand phonon transport across perfect Ga2O3-diamond interface, which in turn sheds light on the possible TBC one could achieve with an optimized interface. A reduced thermal conductivity of the Ga2O3 nano-membrane is also observed due to additional phonon-membrane boundary scattering. The impact of the Ga2O3-substrate TBC and substrate thermal conductivity on the thermal performance of a power device are modeled and discussed. Without loss of generality, this study is not only important for Ga2O3 power electronics applications which would not be realistic without a thermal management solution, but also for the fundamental thermal science of heat transport across Van der Waals bonded interfaces.

While there is a great wealth of data for thermal transport in synthetic diamond, there remains much to be learned about the impacts of grain structure and associated defects and impurities within a few microns of the nucleation region in films grown using chemical vapor deposition. Measurements of the inhomogeneous and anisotropic thermal conductivity in films thinner than 10 μm have previously been complicated by the presence of the substrate thermal boundary resistance. Here, we study thermal conduction in suspended films of polycrystalline diamond, with thicknesses ranging between 0.5 and 5.6 μm, using time-domain thermoreflectance. Measurements on both sides of the films facilitate extraction of the thickness-dependent in-plane (κr) and through-plane (κz) thermal conductivities in the vicinity of the coalescence and high-quality regions. The columnar grain structure makes the conductivity highly anisotropic, with κz being nearly three to five times as large as κr, a contrast higher than that reported previously for thicker films. In the vicinity of the high-quality region, κr and κz range from 77 ± 10 W/m-K and 210 ± 50 W/m-K for the 1 μm thick film to 130 ± 20 W/m-K and 710 ± 120 W/m-K for the 5.6 μm thick film, respectively. The data are interpreted using a model relating the anisotropy to the scattering on the boundaries of columnar grains and the evolution of the grain size considering their nucleation density and spatial rate of growth. This study aids in the reduction in the near-interfacial resistance of diamond films and efforts to fabricate diamond composites with silicon and GaN for power electronics.

A long-standing goal of GaN device research has been the development of a reliable, well-controlled process for p-GaN formation by ion implantation. Results to date have indicated an activation of 1% or less using high-temperature rapid thermal annealing (RTA) techniques and coimplantation. Although Mg is a relatively deep acceptor, this is still much less than the theoretically achievable value (8.2% based on the 160 meV acceptor level). A multicycle RTA process is presented that is capable of achieving up to 8% activation of the Mg-implanted GaN. This approaches the theoretical value, and represents a significant step in GaN device research.

An MOS transistor fabricated on (001) β-Ga 2 O 3 exfoliated from a commercial (−201) β-Ga 2 O 3 substrate is reported. A maximum drain current of 11.1 mA/mm was measured, and a non-destructive breakdown was reached around 80 V in the off state. Threshold voltage of +2.9 V was extracted at 0.1 V drain bias, and peak transconductance of 0.18 mS/mm was measured at V DS = 1 V, corresponding to a field effect mobility of 0.17 cm 2 /Vs. Hall effect and electron spin resonance data suggested that electron conductivity was due primarily to O vacancy donors (V O + ) with an estimated density of 2. The single-crystal monoclinic (β) phase of Ga 2 O 3 is an advantageous material for high-power, high-temperature electronic device applications due to its high energy gap (4.8-4.9 eV) and high breakdown field (8 MV/cm), yielding a nearly ten-fold higher Baliga figure of merit than that of 4H-SiC (BFOM Ga 2 O 3 = 3444, BFOM 4H-SiC = 300).1 Commercially available β-Ga 2 O 3 substrates enable the epitaxial growth of low defect density epitaxial β-Ga 2 O 3 by a number of methods, including chemical vapor deposition, hydride vapor phase epitaxy (HVPE), and molecular beam epitaxy (MBE), among others.2-6 Schottky barrier diodes (SBDs) based on Ga 2 O 3 have exhibited very low turn on voltage and reverse leakage current, suggesting that unintentionally doped Ga 2 O 3 has extremely low generation/recombination rates and thus a high photoconductive gain.7 Advances in doping control have enabled exceptional early reports of metal-and metal-insulatorgated field effect transistors (MOSFETs). Wong et al. demonstrated a field-plated β-Ga 2 O 3 MOSFET with a breakdown voltage of over 750 V using a Si-implanted channel.8 Most recently, Green and coworkers have reported a Ga 2 O 3 MOSFET with a Sn-doped channel and a 0.6 μm gate-drain spacing to operate at 200 V drain bias, experimentally demonstrating gate-drain fields in excess of 3 MV/cm. 9This excellent progress has positioned Ga 2 O 3 as a viable candidate for next generation material for power applications. However, no demonstration of normally-off operation, a key requirement for fail-safe operation of power switches, has been achieved or proposed to-date.From a practical perspective, development of Ga 2 O 3 transistors has been limited by the availability of device-quality epitaxial films. For this reason, early reports have exploited the relatively large a-plane lattice constant of β-Ga 2 O 3 (1.2 nm) in order to mechanically exfoliate thin films from the (001) plane of a substrate using the scotch tape method to fabricate back-gated devices. 10,11 We employed a similar method to transfer a thin (∼300 nm) Ga 2 O 3 flake onto a SiO 2 /Si substrate, 12 and performed a standard top-side insulated-gate process to fabricate a three-terminal device. We also utilized a high-k HfO 2 gate dielectric process, as only SiO 2 and Al 2 O 3 have been reported to-date. 13,14Experimental A thin sliver of Ga 2 O 3 was cleaved along the (001) face of an on-axis (−201), non-intentionally n-type doped (∼3 ×...