This paper proposes an all-digital clock synchronization buffer (CSB) with one-cycle dynamic synchronization. The CSB synchronizes the input and output clocks in three clock cycles but maintains one cycle at fastest operating frequency. The CSB achieves one-cycle dynamic locking and synchronizes the dynamic frequencies with a modified structure. The CSB compensates for dynamic phase error with a modified fine-tuned circuit. The chip is fabricated using a 130-nm standard CMOS process. Its operating frequency range is between 300 MHz and 800 MHz. The power consumption and RMS jitter are 2.4 mW and 2.25 ps at 800 MHz, respectively. The active area of this chip is 0.015 mm .Index Terms-Arbitrary duty cycle, clock synchronization buffer (CSB), fast locking, one cycle dynamic locking, synchronous mirror delay (SMD).
An 8 inch QXGA (1536 * 2048) TFT-LCD panel with integrated gate driver circuit by using a-IGZO process has been fabricated. The border size of panel is 1.8 mm and the power consumption of the proposed gate driver circuit is 60 mW. Moreover, high temperature operation at 70Ԩ within 500 hours without failure shows the useful stabilization of the proposed circuit.
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