A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit

Cheng, Kuo-Hsing; Hong, Kai-Wei; Chen, Chi-Hsiang; Liu, Jen-Chieh

doi:10.1109/tvlsi.2010.2049387

Cited by 16 publications

(6 citation statements)

References 11 publications

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“…Table I summarizes the performance comparison of the proposed ADDLL with the conventional closed-loop ADDLLs. The figure-of-merit (FOM) for power consumption is defined in [15] as where the power consumption is represented in microwatts, the operating frequency is represented in megahertz, and the voltage is represented in square volts. Chip area is also an important parameter for ADDLLs and it has been normalized to channel length and maximum delay in [5].…”

Section: Resultsmentioning

confidence: 99%

An All-Digital Delay-Locked Loop Using an In-Time Phase Maintenance Scheme for Low-Jitter Gigahertz Operations

Wang

Cheng

2015

IEEE Trans. Circuits Syst. I

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Traditional all-digital delay-locked loops (ADDLLs) have a long control loop, and false skew compensation may occur due to late code adjustment. To avoid this problem, the ADDLLs either simply sacrifice the maximum operating frequency or adopt a lower code adjustment rate to achieve a higher maximum operating frequency. However, lowering the code adjustment rate not only increases the number of the locking cycles but also results in large output jitter because the clock skew induced by run-time variations cannot be compensated in time. This paper presents a 55 nm 1.0 V 0.1-to-2.5 GHz ADDLL, which is constructed on a previously proposed half-delay-line skew-compensation circuit with several new circuit design techniques developed to achieve low jitter, small area, low power, fast lock-in, and high PVT-variation tolerance across a large operating frequency range. The key design feature is a ping-pong phase maintenance scheme that allows the code adjustment to be performed in time in each clock cycle, even for gigahertz operations. The measurement results show that the ADDLL achieves a peak-to-peak (p-p) jitter of 3 ps with 1.96 mW power consumption and 8 lock-in cycles when operated at 2.5 GHz.Index Terms-All-digital delay-locked loop (ADDLL), fast lock-in, high frequency, low power, ping-pong phase maintenance scheme, 2b-per-stage asynchronous binary search (2b-ABS).

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Section: Resultsmentioning

confidence: 99%

An All-Digital Delay-Locked Loop Using an In-Time Phase Maintenance Scheme for Low-Jitter Gigahertz Operations

Wang

Cheng

2015

IEEE Trans. Circuits Syst. I

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“…These improvements directly extend its adaptability in the communication system and biomedical system. Table 1 The summary and comparison of the performance EL'09 [6] T-VLSI'09 [5] T-VLSI'13 [7] T-VLSI'11 [2] T-VLSI'12 [1] This Work …”

Section: Resultsmentioning

confidence: 99%

A low supply voltage synchronous mirror delay with quadrature phase output

Cheng

Hsu

et al. 2014

17th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems

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This work proposes a low supply voltage synchronous mirror delay (SMD) circuit with quadrature phase output in intra-chip. In some application-specific integrated chips (ASICs) or silicon intellectual properties (IPs) might enter hibernation mode to conserve energy. The long locking time induces a large standby current, which results in greater power consumption. Furthermore, for some specific applications, the circuits need to operate in a low supply voltage environment. In some communication systems, they even need to have I/Q clock signals. Therefore, this is often led to a synchronous circuit with extra functional capabilities. The proposed SMD with the quadrature delay path can operate in the low supply voltage environment by using the low-voltage techniques. The chip is implemented by TSMC CMOS 1P/9M 90 nm technology with a low supply voltage, 0.5 V. The operation range is from 220 MHz to 570 MHz, and the power consumption is 1.95 mW at 570 MHz. The peak-to-peak jitter and RMS jitter of internal clock are 31.78 ps and 3.99 ps at 570 MHz, respectively. The peak-to-peak jitter and RMS jitter of quadrature internal clock are 34.67 ps and 4.48 ps at 570 MHz, respectively. The core area is 188 × 171 um 2 .

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“…The ability to measure microwave signals with a resolution of few tens of hertz is very attractive to improving noise rejection and precision in a wide variety of applications such as in radar/sonar systems, [8][9][10] clock synchronization, [11,12] remote sensing, [10,13] etc. Apart from such applications, extreme precision in the measurement of phase and amplitude of short wavelength electromagnetic (EM) waves allows us to use the technique to measure other physical quantities with high precision.…”

Section: Generalized Lock-in Amplifiermentioning

confidence: 99%

Note: High precision measurements using high frequency gigahertz signals

Jin

Sakurai

et al. 2014

Review of Scientific Instruments

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Abstract. Generalized lock-in amplifiers use digital cavities with Q-factors as high as 5×10 8 . In this letter, we show that generalized lock-in amplifiers can be used to analyze microwave (giga-hertz) signals with a precision of few tens of hertz. We propose that the physical changes in the medium of propagation can be measured precisely by the ultra-high precision measurement of the signal. We provide evidence to our proposition by verifying the Newton's law of cooling by measuring the effect of change in temperature on the phase and amplitude of the signals propagating through two calibrated cables. The technique could be used to precisely measure different physical properties of the propagation medium, for example length, resistance, etc. Real time implementation of the technique can open up new methodologies of in-situvirtual metrology in material design.

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A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit

Cited by 16 publications

References 11 publications

An All-Digital Delay-Locked Loop Using an In-Time Phase Maintenance Scheme for Low-Jitter Gigahertz Operations

An All-Digital Delay-Locked Loop Using an In-Time Phase Maintenance Scheme for Low-Jitter Gigahertz Operations

A low supply voltage synchronous mirror delay with quadrature phase output

Note: High precision measurements using high frequency gigahertz signals

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