A low supply voltage synchronous mirror delay with quadrature phase output

Abstract

This work proposes a low supply voltage synchronous mirror delay (SMD) circuit with quadrature phase output in intra-chip. In some application-specific integrated chips (ASICs) or silicon intellectual properties (IPs) might enter hibernation mode to conserve energy. The long locking time induces a large standby current, which results in greater power consumption. Furthermore, for some specific applications, the circuits need to operate in a low supply voltage environment. In some communication systems, they even need to have I/Q clock signals. Therefore, this is often led to a synchronous circuit with extra functional capabilities. The proposed SMD with the quadrature delay path can operate in the low supply voltage environment by using the low-voltage techniques. The chip is implemented by TSMC CMOS 1P/9M 90 nm technology with a low supply voltage, 0.5 V. The operation range is from 220 MHz to 570 MHz, and the power consumption is 1.95 mW at 570 MHz. The peak-to-peak jitter and RMS jitter of internal clock are 31.78 ps and 3.99 ps at 570 MHz, respectively. The peak-to-peak jitter and RMS jitter of quadrature internal clock are 34.67 ps and 4.48 ps at 570 MHz, respectively. The core area is 188 × 171 um 2 .

A novel circuit for clock synchronization using binary search scheme and phase interpolation

“…Many advanced circuits utilizing the hybrid structure to 978-1-4673-7005-9 115/$31.00 ©2015 IEEE 56 get fast alignment are proposed [4]- [8]. Time required is much shortened to several clock cycles with an accep table resolution.…”