Oversampled sigma-delta (61) modulators offer numerous advantages for the realization of high-resolution analogto-digital (A/D) converters. This paper explores how oversampling and feedback can be employed in high-resolution 61 modulators to extend the signal bandwidth into the range of several megahertz when the oversampling ratio is constrained by technology limitations. A 2-2-1 cascaded multibit architecture suitable for operation from a 2.5-V power supply is presented, and a linearization technique referred to as partitioned data weighted averaging is introduced to suppress in-band digital-to-analog converter (DAC) errors. An experimental prototype based on the proposed topology has been integrated in a 0.5-m double-poly triple-metal CMOS technology. Fully differential double-sampled switched-capacitor integrators enable the modulator to achieve 95-dB dynamic range at a 4-Msample/s Nyquist conversion rate with an oversampling ratio of 16. The experimental modulator dissipates 150 mW from a 2.5-V supply.Index Terms-Analog-to-digital conversion, CMOS analog integrated circuits, double sampling, dynamic element matching, integrated circuit design, mixed analog-digital integrated circuits, sampled-data circuits, sigma-delta modulation, switched-capacitor circuits.

No abstract

No abstract

No abstract

No abstract