Abshct-A technique for realizing large-scale monolithic OEIC's, which involves epitaxially growing GaAs-based heterostructures on fully metallized commercial VLSI GaAs MES-FET integrated circuits, has recently been reported. In the initial work the circuits and LED's occupied distinct halves of a chip, the dielectric growth window was wet-etched after circuit fabrication, and the LED's required both n and p ohmic contacts to be formed after epitaxial growth. In this letter we report the use of standard foundry process etches to open dielectric growth windows intermixed with circuitry and the growth of n-side-down LED's on a sourcddrain ion-implanted n+ region serving as the n ohmic contact. A winner-take-all neural circuit is demonstrated using these advances, which are important steps toward realizing higher levels of circuit integration.T HAS RECENTLY been reported that fully processed,
Commercially available, self-aligned VLSI GaAs MESFET's, with tungsten-based refractory-metal Schottky gates, nickel-based refractory-metal ohmic contacts, and aluminum interconnection metallization, have been thermally cycled and shown to be stable after 3 h at temperatures up to 500°C. Both partially processed and fully processed wafers were found to be stable with no significant change occurring in either Schottky gate or ohmic contact properties. An increase in the channel resistance component of the series resistance is believed to be responsible for IDS and gm degradation above 500°C. The fact that commercially available, gold-free VLSI GaAs MESFET's are able to withstand such thermal cycles has very important consequences for monolithic optoelectronic integrated circuit (OEIC) fabrication because it means that it may now be feasible to grow photonic device heterostructures epitaxially on MESFET VLSI wafers; process them into lasers, modulators, and/or detectors; and interconnect them with the electronics to produce VLSI-density OEIC's.
Abstract-Fully processed VLSI GaAs MESFET circuits, available through the MOSIS service, have recently been shown to be electrically stable after 3-h thermal cycles at 500°C. It is therefore feasible to epitaxially regrow photonic device heterostructures directly on high-density electronic circuits yielding monolithic optoelectronic VLSI circuits. The MBE growth, planarhation, and LED fabrication of the first optoelectronic circuit using this novel integration technique are described.HE uniformity required for large two-dimensional op-T toelectronic arrays can only be achieved with stateof-the-art technology available at an industrial foundry. In fact, one of the main reasons for the slow development of large-scale two-dimensional optoelectronic arrays is the lack of an industrial foundry for optoelectronics similar to the existing foundries for electroniq silicon circuits. Since there is currently no commercially available foundry for customdesigned optoelectronic circuitry, several groups have built hybrid optoelectronic arrays by taking advantage of an existing foundry for the electronic circuitry and attaching hybrid optical devices afterwards [l], [2]. In this paper we describe how GaAs optical devices can be monolithically integrated with GaAs MESFET-based cisuitry fabricated by Vitesse Semiconductor Co. through MWIS [3].' The fully processed GaAs circuits from MOSIS can withstand temperatures up to 525"flO"C for 3 h without significant changes in performance [4], and therefore it is possible to regrow heterostructures on such circuits to monolithically integrate optical devices such as multiple quantum well (MQW) modulators, light emitting diodes (LED's) and laser diodes.The most general optoelectronic circuit consists of photodetectors, electronic circuitry, and some form of optical output, either an optical source or an optical modulator. The process provided by MOSISNitesse aHows one to design circuits with enhancement-mode (threshold voltage, VT = 0.27V) and Manuscript received November 16, 1993; revised April 27, 1994. This work . The electronic circuit component of the optoelectronic circuit can be designed using standard CAD design and layout tools. The regrowth region is allocated by leaving blank areas where there is no electronic circuitry in the chip design and ultimately removing the dielectric layers in these regions so that the wafer surface is exposed. Fig. 1 shows the chip cross section of the optoelectronic circuit. The transistor circuits are ion-implanted GaAs MESFET circuits with tungsten-based refractory metal Schottky gates, nickelbased refractory metal ohmic contacts, and three levels of aluminum interconnect metallization. Two of the metal levels are used for signal routing and the third for power distribution. The total thickness of the dielectric stack, used to separate the various aluminum interconnect metal, is approximately 4pm. To determine the uniformity of the MESFET's, the drain-source current of 20 depletion-mode MESFET's ( L = 2.8 pm, W = 13.6 pm) was measured with the g...
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