The paper presents the results of the development of a package-on-package multichip microcircuit with three-dimensional integration of processor and memory dies. The stages of fabrication the upper part of the microcircuit with several memory dies, which are mounted by the wire bonding method, and the lower part of the microcircuit, on which the processor die is attached by the flip-chip method, are described. After the fabrication of the microcircuit by combining the upper and lower substrates, a multi-stage functional testing of the processor and memory dies is performed using a test board and software loaded into the microcircuit memory.
The paper provides a technical solution and methodology for conducting automated electrical and functional testing of small series samples of multi-chip assemblies. The results of multi-chip assembly samples testing combining Wire Bond and Flip-Chip technologies are presented. Based on the test results, defects that occur during the packaging process are localized and the assembly stages at which these defects occur are determined.
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