A MOS transistor with a channel length under 0.20 im was developed with the process equipment typically utilized for a conventional 2 im device. The transistor was built on the vertical side walls of a 3 dimensional trench, thus achieving much higher channel width W, and lower channel length L than possible using 2im planar technology. The capability of having larger W coupled with non-photolithography limited L, gives this vertical MOS transistor great advantages in drain current 'DS, transconductance g, Lfld operation frequency f0 over same technology planar transistors.
A sub 0.1 microns channel length vertical MOS transistor was developed for processing with equipment typically utilized for older generation devices. One of the important advantages of vertical MOS transistor technology is that the channel length scaling is not limited by the minimum lithographic resolution. The vertical Ldd processing was also developed to improve the short channel effects. The transistor with channel length below 0. 1 tm has normal characteristics at room temperature, a >6V Bvdss, and a Iransconductance with value as high as in the conventional planar transistor of the same channel length.Short channel length MOS transistors are always desired for ULSI devices with higher packing density, and much
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