Sub-half-micron device fabricated with 2-μm generation facilities

Abstract

A MOS transistor with a channel length under 0.20 im was developed with the process equipment typically utilized for a conventional 2 im device. The transistor was built on the vertical side walls of a 3 dimensional trench, thus achieving much higher channel width W, and lower channel length L than possible using 2im planar technology. The capability of having larger W coupled with non-photolithography limited L, gives this vertical MOS transistor great advantages in drain current 'DS, transconductance g, Lfld operation frequency f0 over same technology planar transistors.

Sub-0.1-μm vertical MOS transistor

“…The VMOS transistor [1] with 1 im vertical channel was among the first studies in this field, and a number ofproposals [2,3,4,5,6,7,9Jhave since been made for sub-micron vertical MOS transistors. Photolithography technologies currently used for patterning submicron channel length MOS transistors are quickly approaching practical and fundamental limits.…”