The rapid progress of multimedia demands liquid crystal display (LCD) projectors that can display computer data, such as videographic arrays (VGA; 640x480 pixels), super-video-graphic arrays (SVGA, 800x600 pixels), extended-graphic arrays (XGA, 1024x768 pixels) and super-extended-graphic arrays (SXGA, 1280x1024 pixels). One of the major challenges for poly-Si TFT drivers in such multi-scan LCDs is displaying as black in the peripheral region around the picture during a blanking period. Using conventional shift register driver circuits, the scanning speed in the up-and-down no-picture region is too high for pixel TFTs to write signals for black. Although decoder driver circuits for multi-scan operation have been introduced into an HDTV poly-Si TFT-LCD [l], they require many address signals and logic gates. These increase circuit area and thereby decrease the manufacturing yields. Poly-Si TFT drivers use a combination of bi-directional shift registers and decoder circuits to solve the above problems for a 2.7in, 1.3Mpixel T I 3 LCD light valve. Figure 1 shows a schematic diagram of the driver-integrated polySi TFT-LCD light valve. The scan and data drivers are located redundantly on both sides to improve the yield and to shorten the signal delay in the scan and data lines. Since both the scan and data drivers include bi-directional shift registers, the light valve has an up-and-down and left-and-right image-reversing function. This function allows use of the light valve for both front-and reartype projectors. The scan and data drivers are driven by 14 and 11 control signals, respectively. There are video signal inputs of 24. Figure 2 shows the scan driver circuit diagram. The scan driver consists of a 256b bi-directional shift register, a decoder circuit, and output buffers. The bi-directional shift register is composed of transmission gates and feedback circuits. The feedback circuits prevent the amplitude of the transferred signals from decreasing. The shift register needs no additional TFTs for exchanging the shift direction; this improves the circuit speed and the circuit yield. The shift register is capable of operating at 50MHz at a supply voltage of 18V. Shift direction can be exchanged by changing a combination of the clock signals, GA through GD. For down-shift, GA (GB) and GD (GC) are the same, whle for up-shift, GA (GB) and GC (GD) are the same. The decoder NAND gates are controlled by outputs of the shift register and eight control signals, G1 through G8. The number of TFTs in the scan driver is only 13 per scan line. This circuit scale is smaller than that of conventional shift register drivers for non-multi-scan LCDs. Figure 3 shows the data driver circuit diagram. The data driver consists of a 27b bi-directional shift register, a decoder circuit, NAND gate switches, output buffers, and analog switches. The NAND gates in the decoder circuit are controlled by the shiftregister outputs and four control signals, D 1 through D4. The NAND gate switches controlled by an output control signal are used for tu...
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