A 1440×1080 pixels 30frames/s motion-JPEG2000 codec for HD movie transmission

Yamauchi, Hironori; Mochizuki, K.; Taketa, K.; Watanabe, Takanori; Mori, Takeshi; Matsuda, Yoshihisa; Matsushita, Y.; Kobayashi, Akira; Okada, S.

doi:10.1109/isscc.2004.1332726

Cited by 8 publications

(9 citation statements)

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“…Therefore, not only the the EBC is the throughput bottleneck of the entire system but also the multiple memory accesses for DWT coefficients due to EBC's sequential property introduce the waste of power consumption. Due to the two critical problems, the previous architectures [23], [12], [24] use tile-level pipeline scheduling, i.e., the EBC processes the current tile while the DWT processes the next tile in the encoder system by using tile memory. For the target specification 1920 1080 4:2:2 30 fps and tile size 256 256, it costs 175 kB ( bits) memory requirement for storing 10-bit DWT coefficients of two tiles and 310 MB/s ( ) coefficients transmission between the DWT and the EBC.…”

Section: Level-switched Schedulingmentioning

confidence: 99%

“…However, the complexity of JPEG 2000 is much higher than that of JPEG. Several JPEG 2000 codec designs have been reported in the literature [1], [8], [23], [24]. However, they suffer from either high operating frequency or large chip area.…”

mentioning

confidence: 99%

“…The design of [1] occupies 144 mm to achieve about 50 MS/s throughput. Sanyo [23], [24] developed an efficient JPEG 2000 codec architecture, which compromises between the throughput and the silicon area while keeping the operating frequency as low as 54 MHz. However, the SDRAM bandwidth requirement is so high that two buses are needed, and the operating frequency of each bus is two times that of the core.…”

mentioning

confidence: 99%

“…Therefore, a tile memory is usually used for transferring coefficients between the DWT and the EBC. Tile-level pipeline scheduling introduces either high bandwidth for those architectures storing tiles in off-chip memory [23], [24] or high cost for those architectures storing tiles in on-chip memory.…”

mentioning

confidence: 99%

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124 MSamples/s Pixel-Pipelined Motion-JPEG 2000 Codec Without Tile Memory

Chang

Cheng

Chen

et al. 2007

IEEE Trans. Circuits Syst. Video Technol.

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Section: Level-switched Schedulingmentioning

confidence: 99%

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confidence: 99%

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confidence: 99%

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confidence: 99%

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124 MSamples/s Pixel-Pipelined Motion-JPEG 2000 Codec Without Tile Memory

Chang

Cheng

Chen

et al. 2007

IEEE Trans. Circuits Syst. Video Technol.

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“…JPEG 2000 [19] can achieve very good coding efficiency with higher complexity. The reported JPEG 2000 codec chips all have die sizes above 20mm 2 with 0.18µm technology [20] [21] [22]. If JPEG 2000 algorithm is adopted for embedded compression, only the tile buffer between DWT and EBCOT will require more than 30000 logic gates.…”

Section: A Overview Of Spiht Algorithmmentioning

confidence: 99%

Multi-mode embedded compression codec engine for power-aware video coding system

Cheng¹,

Tseng²,

Huang³

et al.

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.

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Abstract-In a typical portable multi-media system, external access, which is usually dominated by block-based video content, induces more than half of total system power. Embedded compression (EC) effectively reduces external access caused by video content by reducing the data size. In this paper, an algorithm and a hardware architecture of a new type EC codec engine with multiple modes are presented. Lossless mode, and lossy modes with rate control modes and quality control modes are all supported by single algorithm. The proposed four-tree pipelining scheme can reduce 83% latency and 67% buffer size between transform and entropy coding. The proposed EC codec engine can save 62%, 66%, and 77% external access at lossless mode, half-size mode, and quarter-size mode and can be used in various system power conditions. With TSMC 0.18 µm 1P6M CMOS logic process, the proposed EC codec engine can encode or decode CIF 30 frame per second video data and achieve power saving of more than 109mW. The EC codec engine itself consumes only 2mW power.

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Memory Efficient JPEG 2000 Architecture with Stripe Pipeline Scheme

Fang¹,

Chang²,

Cheng³

et al.

Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005.

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Memory issue is the most critical problem for a high performance JPEG 2000 architecture. The tile memory occupies more than 50% of area in conventional JPEG 2000 architectures. To solve this problem, we propose a stripe pipeline scheme. For this scheme, a Level Switch Discrete Wavelet Transform (LS-DWT) and a Codeblock Switch Embedded Block Coding (CS-EBC) are proposed. With small additional memory, the LS-DWT and the CS-EBC can process multiple levels and code-blocks in parallel by an interleaved scheme. As a result of above techniques, the overall memory requirements of the proposed architecture can be reduced to only 8.5% comparing with conventional architectures.

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A 1440×1080 pixels 30frames/s motion-JPEG2000 codec for HD movie transmission

Cited by 8 publications

References 0 publications

124 MSamples/s Pixel-Pipelined Motion-JPEG 2000 Codec Without Tile Memory

124 MSamples/s Pixel-Pipelined Motion-JPEG 2000 Codec Without Tile Memory

Multi-mode embedded compression codec engine for power-aware video coding system

Memory Efficient JPEG 2000 Architecture with Stripe Pipeline Scheme

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