This paper presents the gate capacitance characteristics of the gatem-overlap LDD transistor with high performance and high reliability. The gate capacitance was directly measured by a four terminal method, using a LCR meter. The measured results for the overlap LDD were compared with those for the single drain and the LDD structure. It was demonstrated that the gate/drain capacitance for the overlap LDD is smaller than that for the single drain and as small as that for the LDD in spite of the large overlap length between the gate and the N-region. This experimental result was also confirmed by the simulation, which clarifies that the small gate/drain capacitance of the overlap LDD is due to the depletion of the N-drain under the gate by the normal electric field fmm the gate and the lateral electric field at the drain.
ABSTRACf This paper presents the improvement of 0.5 urn gate CMOS. The CMOS features an overlap LDD NMOS and a surface channel LDD PMOS with p + poly gate both of which source/drain and gate were salicided with low resistive TiSi2. This CMOS structure can realize low supply voltage operation due to the small absolute value of threshold voltage without punch-through. It is demonstrated that employing the overlap LDD NMOS, the circuit speed and the reliability can be improved, compared with the single and the conventional LDD NMOS. With the CMOS consisting of the overlap LDD NMOS and the surface channel PMOS, the cryogenic operation is also examined.
In this paper an experimental study of the scalability of a gate/N- overlapped lightly doped drain (OL-LDD) structure in the deep-submicrometer regime is presented. Devices were optimized for processes with a design rule down to 0.15 µm. The allowable power
supply voltage is obtained by investigating the time-dependent dielectric breakdown reliability, the minimum operating voltage, the gate-induced-drain-leakage current, the drain-induced-barrier-lowering effect and the DC hot carrier reliability. It was found that the maximum allowable supply voltage is mainly limited by the DC hot carrier reliability even in the deep-submicrometer range. A higher current-driving ability in the OL-LDD structure is achieved in comparison to that in a single drain (SD) structure when V
Dmax is applied as a supply voltage. The OL-LDD structure has a smaller C
GD in the inversion region as well as in the accumulated region, as compared with the SD structure, especially with smaller L
G. Consequently, the performance of complementary metal-oxide-semiconductor (CMOS) devices with the OL-LDD structure is superior to that with the SD structure in the deep-submicrometer regime. It is also confirmed that the OL-LDD structure has a scaling merit even for 0.15 µm CMOS devices.
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