Differential caseode voltage switch (DCVS) logic is a CMOS circuit technique which has potential advantages over conventional NAND/ NOR logic in terms of circuit delay, layout density, power dissipation, aud logic flexibility. In this paper a detailed comparison of DCVS logic and conventional logic is carried out by simulation, using SPICE, of the performance of fnfl adders designed using the different circuit techniques. Specifically, comparisons are made between a static full CMOS design and two different implementations of static DCVS circuits, and, in the dyuamic case, between two conventional NORA implementations and DCVS forms of both NORA and DOMINO logic. The parameters compared are input gate capacitance, number of transistors required, propagation delay time, and average power dissipation.
Differential cascode voltage switch (DCVS) logic is a CMOS circuit technique which has potential advantages over conventional NAND/ NOR logicin terms of circuit delay, layout density, power dissipation, and logic flexibility. In this paper, two procedures are presented for constricting DCVS trees to perform random logic functions. The first procedure uses a Karnaugh mapping technique and is a very powerful pictorial method for hand-proeessing designs involving up to six variables. The second procedure is a tabular method based on the Quine-McCluskey approach and is suitable for functions with more thansixvariables. Bothof these procedures are considerably easier to implement than a recently proposed algebraic technique which relies upon decomposition and factorization of Boolean expressions. Several DCVS circuits that have been synthesized by the Karnaugh map (K-map) and tabular procedures are presented.
Calculations are reported of the series resistance caused by the thin insulating layer which separates the polycrystalline and monocrystalline regions of the emitter in certain types of polysilicon emitter transistors. It is demonstrated that the series resistance depends on the shape of the potential barrier which characterizes the thin insulator. For a triangular barrier the series resistance may be low enough for the transistors to be acceptable for very large scale integrated circuit applications.
The Electro-Optics Laboratory of the Institute for Space and Terrestrial Science characterizes array detectors under a wide range of operating conditions in a test facility based on a uniform optical source, a flexible array controller, a cryostat and comprehensive data acquisition hardware and software.Source characteristics, ambient temperature, clock/bias parameters and output signal conditioning can be varied to maximize the useful information about the devices under test.Emphasis has been placed on achieving a high level of accuracy and reproducibility in the measurements.Results from representative CCD arrays are used to illustrate design highlights and facility capabilities.
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