The formation of MoO(3) sheets of nanoscale thickness is described. They are made from several fundamental sheets of orthorhombic alpha-MoO(3), which can be processed in large quantities via a low cost synthesis route that combines thermal evaporation and mechanical exfoliation. These fundamental sheets consist of double-layers of linked distorted MoO(6) octahedra. Atomic force microscopy (AFM) measurements show that the minimum resolvable thickness of these sheets is 1.4 nm which is equivalent to the thickness of two double-layers within one unit cell of the alpha-MoO(3) crystal.

The advantages of printed electronics and semiconducting single-walled carbon nanotubes (SWCNTs) are combined for the first time for display electronics. Conductive silver ink and 98% semiconductive SWCNT solutions are used to print back-gated thin film transistors with high mobility, high on/off ratio, and high current carrying capacity. In addition, with printed polyethylenimine with LiClO4 as the gating material, fully printed top-gated devices have been made to work as excellent current switches for organic light emitting diodes (OLEDs). An OLED driving circuit composed of two top-gated fully printed transistors has been fabricated, and the successful control over external OLED is demonstrated. Our work demonstrates the significant potential of using printed carbon nanotube electronics for display backplane applications.

This paper presents aligned carbon nanotube (CNT) synaptic transistors for large-scale neuromorphic computing systems. The synaptic behavior of these devices is achieved via charge-trapping effects, commonly observed in carbon-based nanoelectronics. In this work, charge trapping in the high- k dielectric layer of top-gated CNT field-effect transistors (FETs) enables the gradual analog programmability of the CNT channel conductance with a large dynamic range ( i. e., large on/off ratio). Aligned CNT synaptic devices present significant improvements over conventional memristor technologies ( e. g., RRAM), which suffer from abrupt transitions in the conductance modulation and/or a small dynamic range. Here, we demonstrate exceptional uniformity of aligned CNT FET synaptic behavior, as well as significant robustness and nonvolatility via pulsed experiments, establishing their suitability for neural network implementations. Additionally, this technology is based on a wafer-level technique for constructing highly aligned arrays of CNTs with high semiconducting purity and is fully CMOS compatible, ensuring the practicality of large-scale CNT+CMOS neuromorphic systems. We also demonstrate fine-tunability of the aligned CNT synaptic behavior and discuss its application to adaptive online learning schemes and to homeostatic regulation of artificial neuron firing rates. We simulate the implementation of unsupervised learning for pattern recognition using a spike-timing-dependent-plasticity scheme, indicate system-level performance (as indicated by the recognition accuracy), and demonstrate improvements in the learning rate resulting from tuning the synaptic characteristics of aligned CNT devices.

The semiconductor industry will soon be launching 32 nm complementary metal oxide semiconductor (CMOS) technology node using 193 nm lithography patterning technology to fabricate microprocessors with more than 2 billion transistors. To ensure the survival of Moore's law, alternative patterning techniques that offer advantages beyond conventional top-down patterning are aggressively being explored. It is evident that most alternative patterning techniques may not offer compelling advantages to succeed conventional top-down lithography for silicon integrated circuits, but alternative approaches may well indeed offer functional advantages in realising next-generation information processing nanoarchitectures such as those based on cellular, bioinsipired, magnetic dot logic, and crossbar schemes. This paper highlights and evaluates some patterning methods from the Center on Functional Engineered Nano Architectonics in Los Angeles and discusses key benchmarking criteria with respect to CMOS scaling.