Janus crystals represent an exciting class of 2D materials with different atomic species on their upper and lower facets. Theories have predicted that this symmetry breaking induces an electric field and leads to a wealth of novel properties, such as large Rashba spin–orbit coupling and formation of strongly correlated electronic states. Monolayer MoSSe Janus crystals have been synthesized by two methods, via controlled sulfurization of monolayer MoSe2 and via plasma stripping followed thermal annealing of MoS2. However, the high processing temperatures prevent growth of other Janus materials and their heterostructures. Here, a room‐temperature technique for the synthesis of a variety of Janus monolayers with high structural and optical quality is reported. This process involves low‐energy reactive radical precursors, which enables selective removal and replacement of the uppermost chalcogen layer, thus transforming classical transition metal dichalcogenides into a Janus structure. The resulting materials show clear mixed character for their excitonic transitions, and more importantly, the presented room‐temperature method enables the demonstration of first vertical and lateral heterojunctions of 2D Janus TMDs. The results present significant and pioneering advances in the synthesis of new classes of 2D materials, and pave the way for the creation of heterostructures from 2D Janus layers.

This paper presents aligned carbon nanotube (CNT) synaptic transistors for large-scale neuromorphic computing systems. The synaptic behavior of these devices is achieved via charge-trapping effects, commonly observed in carbon-based nanoelectronics. In this work, charge trapping in the high- k dielectric layer of top-gated CNT field-effect transistors (FETs) enables the gradual analog programmability of the CNT channel conductance with a large dynamic range ( i. e., large on/off ratio). Aligned CNT synaptic devices present significant improvements over conventional memristor technologies ( e. g., RRAM), which suffer from abrupt transitions in the conductance modulation and/or a small dynamic range. Here, we demonstrate exceptional uniformity of aligned CNT FET synaptic behavior, as well as significant robustness and nonvolatility via pulsed experiments, establishing their suitability for neural network implementations. Additionally, this technology is based on a wafer-level technique for constructing highly aligned arrays of CNTs with high semiconducting purity and is fully CMOS compatible, ensuring the practicality of large-scale CNT+CMOS neuromorphic systems. We also demonstrate fine-tunability of the aligned CNT synaptic behavior and discuss its application to adaptive online learning schemes and to homeostatic regulation of artificial neuron firing rates. We simulate the implementation of unsupervised learning for pattern recognition using a spike-timing-dependent-plasticity scheme, indicate system-level performance (as indicated by the recognition accuracy), and demonstrate improvements in the learning rate resulting from tuning the synaptic characteristics of aligned CNT devices.

In this work, we study the high critical breakdown field in β-Ga2O3 perpendicular to its (100) crystal plane using a β-Ga2O3/graphene vertical heterostructure. Measurements indicate a record breakdown field of 5.2 MV/cm perpendicular to the (100) plane that is significantly larger than the previously reported values on lateral β-Ga2O3 field-effect-transistors (FETs). This result is compared with the critical field typically measured within the (100) crystal plane, and the observed anisotropy is explained through a combined theoretical and experimental analysis.

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Recent studies of resistive switching devices with hexagonal boron nitride (h-BN) as the switching layer have shown the potential of two-dimensional (2D) materials for memory and neuromorphic computing applications. The use of 2D materials allows scaling the resistive switching layer thickness to sub-nanometer dimensions enabling devices to operate with low switching voltages and high programming speeds, offering large improvements in efficiency and performance as well as ultra-dense integration. These characteristics are of interest for the implementation of neuromorphic computing and machine learning hardware based on memristor crossbars. However, existing demonstrations of h-BN memristors focus on single isolated device switching properties and lack attention to fundamental machine learning functions. This paper demonstrates the hardware implementation of dot product operations, a basic analog function ubiquitous in machine learning, using h-BN memristor arrays. Moreover, we demonstrate the hardware implementation of a linear regression algorithm on h-BN memristor arrays.