This paper describes a 160 MHz 500 mW StrongARM microprocessor designed for lowpower, low-cost applications. The chip implements the ARM V4 instruction set 1 and is bus compatible with earlier implementations. The pin interface runs at 3.3 V but the internal power supplies can vary from 1.5 to 2.2 V, providing various options to balance performance and power dissipation. At 160 MHz internal clock speed with a nominal Vdd of 1.65 V, it delivers 185 Dhrystone 2.1 MIPS while dissipating less than 450 mW. The range of operating points runs from 100 MHz at 1.65 V dissipating less than 300 mW to 200 MHz at 2.0 V for less than 900 mW. An on-chip PLL provides the internal clock based on a 3.68 MHz clock input. The chip contains 2.5 million transistors, 90% of which are in the two 16 kB caches. It is fabricated in a 0.35-m three-metal CMOS process with 0.35 V thresholds and 0.25 m effective channel lengths. The chip measures 7.8 mm ϫ 6.4 mm and is packaged in a 144-pin plastic thin quad flat pack (TQFP) package.

IntroductionAs personal digital assistants (PDA's) move into the next generation, there is an obvious need for additional processing power to enable new applications and improve existing ones. While enhanced functionality such as improved handwriting recognition, voice recognition, and speech synthesis are desirable, the size and weight limitations of PDA's require that microprocessors deliver this performance without consuming additional power. The microprocessor described in this paper-the Digital Equipment Corporation SA-110, the first microprocessor in the StrongARM family-directly addresses this need by delivering 185 Dhrystone 2.1 MIPS while dissipating less than 450 mW. This represents a significantly higher performance than is currently available at this power level. CMOS Process TechnologyThe chip is fabricated in a 0.35 m three-metal CMOS process with 0.35 V thresholds and 0.25 µm effective channel lengths. Process characteristics are shown in Table 1. The process is the result of several generations of development efforts directed toward highperformance microprocessors. It is identical to the one used in Digital Equipment Corporation's current generation of Alpha chips 2 except for the removal of the fourth layer of metal and the addition of a final nitride passivation required for plastic packaging.The factors which drive process development for low-power design are similar to those which drive the process for pure high-performance although the motivation sometimes differs. For example, while both types of designs benefit from maximizing Idsat of the transistors at the lowest acceptable Vdd, the motivation for a pure high-performance design is reducing power distribution and thermal problems rather than extending battery life. Similar arguments apply to minimizing transistor leakage and on-chip variation of transistor parameters. This convergence of goals has been essential to our ability to develop one process to satisfy the requirements of both low-power and high-performance families.

The Broadcom BCM12500 is a high performance system on a chip (SOC) targeted at network centric tasks. The chip consists of two high performance SB-1 MIPS64m CPU's, a shared 512KB L2 cache, a DDR memory controller, and integrated UO. All major blocks of the processor are connected together via the ZBbusTM; a high speed split transaction fully coherent multi processor bus.Three Gigabit Ethernet MAC's enable a direct interface to network elements. High-speed system U 0 is provided using AMD's Lightning Data Transport (LDTm) U 0 fabric and a 66MHz PCI bus. The die measures 14.2" by 13.3" in a bulk 0.15pm CMOS technology and has a power dissipation of 13W at 1.2V and 1GHz.

This paper describes a parallel architecture implementation of a Gold code generator for a spread-spectrum communication system and its associated switcli niinimizatioii algorithm. The parallel architecture dissipates less power than the conventional architecture based on serial linear feedback shift registers (LFSR) and also ailons a higher throughput rate conapared bo the serial one nlicre only one bit is generated per clock cycle. The Gold code generator implemented in a 2 micron CMOS technology consunics l e s than 1000 microwatts when clocked at 50 MHz. (21 M.Lowy uid J.J. licmmn, *' Low power, High-Spccd Digital Spread Spcc~ruiii Systcms". Mch.lillan, 1985. CMOS CircuiL<". iii VLSI Signal Processing, V, K. Yao. R. Jain, W. Pnytula and 1. Rahucy eds., IEEE New York. N.Y.