A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor

Montanaro, J.; Witek, Richard T.; Anne, K.; Black, Andrew J.; Cooper, Elizabeth; Dobberpuhl, D.; Donahue, P.; Eno, J.; Hoeppner, W.; Kruckemyer, David; Lee, T.H.; Lin, Pei-Yi; Madden, Lachlan; Murray, D.; Pearce, M.; Santhanam, S.; Snyder, Kathryn J.; Stehpany, R.; Thierauf, Stephen C.

doi:10.1109/jssc.1996.542315

Cited by 453 publications

(134 citation statements)

References 4 publications

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“…The latched comparator topology is a PMOS StrongArm [22] with a resistive load differential pre-amplifier. This pre-amplifier includes an auxiliary differential pair for offset calibration purposes [9].…”

Section: Design Of the 6-bit Single Sar Adcmentioning

confidence: 99%

A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques

Reyes

Paulina²,

Sánchez³

et al. 2015

Analog Integr Circ Sig Process

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A 2-GS/s 6-bit time interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) is designed and fabricated in a 0.13 lm CMOS process. The architecture uses 8 time-interleaved track-andhold amplifiers (THA) and 16 asynchronous SAR ADCs. The sampling frequency of the TI-ADC can be set from 200 MHz to more than 2 GHz. The chip includes a programmable delay cell array to adjust up to AE25 % the sampling clock phase in each THA, and a multi-channel low voltage differential signaling interface capable of transmitting at full sampling rate (>12 Gb/s), without decimation, off-chip. These blocks make the fabricated ADC an excellent platform to test/evaluate mixed-signal calibration algorithms, which are of great interest for application in high-speed optical systems. Measurements of the fabricated ADC show a peak signal-to-noise-and-distortion ratio of 33.9 dB and a power consumption of 192 mW at 1.2 V.

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Section: Design Of the 6-bit Single Sar Adcmentioning

confidence: 99%

A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques

Reyes

Paulina²,

Sánchez³

et al. 2015

Analog Integr Circ Sig Process

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show abstract

“…The comparator in the SDM is a typical dynamic comparator that consists of a latched amplifier and an RS latch [21]. The comparator has relaxed requirement on the offset, so that no preamplifier is needed.…”

Section: Comparatormentioning

confidence: 99%

A microphone readout interface with 74-dB SNDR

Odame

2014

Analog Integr Circ Sig Process

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A continuous-time (CT) sigma-delta modulator (SDM) for condenser microphone readout interfaces is presented in this paper. The CT SDM can accommodate a single-ended input and has high input impedance, so that it can be directly driven by a single-ended condenser microphone. A current-sensing boosted OTA-C integrator with capacitive feedforward compensation is employed in the CT SDM to achieve high input impedance and high linearity with low power consumption. Fabricated in a 0:35-lm complementary metal-oxide-semiconductor (CMOS) process, a circuit prototype of the CT SDM achieves a peak signal-to-noise-and-distortion ratio of 74.2 dB, with 10-kHz bandwidth and 801-lW power consumption.

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“…In order to achieve a fast clock cache, the cache system is implemented as SRAM, which consumes up to 25% and 43% of the total power for the Alpha 21164 [3] and the StrongARM-110 [4] , respectively. Consequently, to reduce energy consumption of cache systems should be carefully considered in the development of a low power microprocessor.…”

Section: Introductionmentioning

confidence: 99%

Energy Efficiency of a Multi-Core Processor by Tag Reduction

Zheng

Dong

Ota

et al. 2011

J. Comput. Sci. Technol.

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We consider the energy saving problem for caches on a multi-core processor. In the previous research on low power processors, there are various methods to reduce power dissipation. Tag reduction is one of them. This paper extends the tag reduction technique on a single-core processor to a multi-core processor and investigates the potential of energy saving for multi-core processors. We formulate our approach as an equivalent problem which is to find an assignment of the whole instruction pages in the physical memory to a set of cores such that the tag-reduction conflicts for each core can be mostly avoided or reduced. We then propose three algorithms using different heuristics for this assignment problem. We provide convincing experimental results by collecting experimental data from a real operating system instead of the traditional way using a processor simulator that cannot simulate operating system functions and the full memory hierarchy. Experimental results show that our proposed algorithms can save total energy up to 83.93% on an 8-core processor and 76.16% on a 4-core processor in average compared to the one that the tag-reduction is not used for. They also significantly outperform the tag reduction based algorithm on a single-core processor.

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A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor

Cited by 453 publications

References 4 publications

A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques

A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques

A microphone readout interface with 74-dB SNDR

Energy Efficiency of a Multi-Core Processor by Tag Reduction

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