Introduction:We report measurements of the DC characteristics of sub-l00nm nMOSFETs that employ low leakage. ultra-thin gate oxides only 1 -2nm thick to achieve high current drive capability and transconductance. We demonstrate that ZDsctr=: 1.8mAIp.m can be achieved with a 60nm gate at 1.5V using a 1.3-1.4nm gate oxide with a gate leakage current less than 20r~AIp.m~. Furthermore, we find that ZDscrr deteriorates for gate oxides thicker or thinner than this.Fabrication: We have explored a gate stack consisting of l00nm of TEOS hard mask over 80nm of doped W.5, on 1 00nm of in-situ phosphorus-doped poly-crystalline silicon on gate oxides ranging in thickness from 1 -2nm thick on a ptype epitaxial silicon. Prior to the oxide growth, the substrates were stripped by immersion into a 15: 1 H 2 0: HF solution for only 5 seconds (to minimize surface roughness and pitting) and then subjected to a vapor phase clean in 10 Torr
We report on integrated, silicon single-nanowire diodes. Gold catalyst templates, defined by lithography, controlled the location of nanowires grown with a vapor-liquid-solid mechanism. The nanowire growth, by atmospheric-pressure chemical vapor deposition, used SiCl4 diluted in H2 on (100) n-type silicon substrates. Postgrowth oxidation and wet etching reduced the nanowire diameters and removed unintentional small diameter nanowires. Spin-on glass isolated the nanowire tips from the substrate, which were then contacted with aluminum. Current-voltage measurements show rectification and ideality factors consistent with pn junction diodes. However, the gold catalyzed nanowires have much higher than expected hole concentrations that cannot be explained by behaviors reported for gold diffused into silicon.
Silicon nanowires, nanoplatelets, and other morphologies resulted from silicon growth catalyzed by thin titanium layers. The nanowires have diameters down to 5 nm and lengths to tens of micrometers. The two-dimensional platelets, in some instances with filigreed, snow flake-like shapes, had thicknesses down to the 10 nm scale and spans to several micrometers. These platelets grew in a narrow temperature range around 900 celsius, apparently representing a new silicon crystallite morphology at this length scale. We surmise that the platelets grow with a faceted dendritic mechanism known for larger crystals nucleated by titanium silicide catalyst islands
IV-measurements were performed on integrated silicon nanowires grown via atmospheric vapor phase epitaxy. The silicon nanowires were grown on a n-type substrate using gold catalysts, insulated using a spin-on glass, and contacted using aluminum. Rectifying behavior and low recombination is observed in the nanowire with a forward bias.
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