The computation of the sine and cosine functions is required in devices ranging from application-specific signal processors to general purpose floating-point units. Even in the latter case, the required functionality can be reduced to computing the sine and/or cosine of multiples of a constant angle. The latency of a sine/cosine generator can be reduced by using look-up tables. However, a direct implementation with look-up tables may be unfeasible if the input space is huge. In such a case, look-up tables with a number of entries lower than the size of the input space can be used indirectly. In previously published methods, the reduction in the number of table entries is obtained at the expense of increasing the table width and the computational cost. This paper introduces an alternative technique that makes it possible to reduce the size of the look-up tables as well as the required multiplications. The proposed technique can be used to implement sine/cosine generators of huge input space. It has been used to implement several twiddle factor generators in reconfigurable hardware and has enabled the number of look-up tables to be reduced by between 6 and 26% with respect to previous table-based techniques. Also, these implementations are about 50% faster than those based on Volder’s algorithm.
Abstract. The verification of the timing requirements of large VLSI circuits is generally performed by using simulation or timing analysis on eachcombinational block of the circuit. Akey factor in timing analysis is the election of the delaymodel type.Pin-to-pin delaymodels are usually employed, but their application is limited in timing analysis when dealing with floating mode or complex gates. This paper does not introduce a delaym odel but ad elaym odel type called Transistor Path DelayM odel (TPDM). This new type of delaym odel is specially useful for timing analysis in floating mode, since it is not required to knowt he whole input sequence to apply it, and can manage complex CMOS gates. An algorithm to get upper bounds on the stabilization time of eachg ate output using TPDM is also introduced.
1Intro ductionOne of the most importanttasks in the design process of VLSI circuits is the verification of the system. Timing verification may beperformed by electric-level P.
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