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Abstract-We show that a nanophotonic silicon-on-insulator (SOI) platform offers many advantages for the implementation of planar concave grating (PCG) demultiplexers, as compared with other material systems. We present for the first time the design and measurement results of a PCG demultiplexer fabricated on a nanophotonic SOI platform using standard wafer scale CMOS processes including deep-UV lithography. Our PCG device has four wavelength channels with a channel spacing of 20 nm and a record-small footprint of 280 × 150 µm. The on-chip loss is 7.5 dB, and the crosstalk is better than −30 dB.

The process of bonding InP/InGaAsP dies to a processed silicon-on-insulator wafer using sub-300 nm layers of DVS-bisbenzocyclobutene ͑BCB͒ was developed. The planarization properties of these DVS-bis-BCB layers were measured and an optimal prebonding die preparation and polymer precure are presented. Bonding quality and bonding strength are assessed, showing high-quality bonding with sufficient bonding strength to survive postbonding processing. Silicon-on-insulator ͑SOI͒ is a material system that is gaining importance in semiconductor electronics industry for low power and high performance operation. Also in integrated optics it is an emerging technology platform. This is due to the fact that the refractive index contrast between the silicon waveguide core and the SiO 2 cladding is high ͑⌬n Х 2͒. This allows making very compact integrated optical functions leading to large-scale integration of optical functions. Moreover, these optical components can be fabricated using standard complementary metal oxide semiconductor ͑CMOS͒ technology, improving the yield, reliability, and economy of scale. 1Although silicon is an interesting material for passive optical functions ͑optical filters, waveguiding, etc.͒ above 1.1 m, where the material is transparent, it has an indirect bandgap and therefore is an inefficient light emitter. In order to integrate both active optical functions ͑laser emission, amplification, detection͒ and passive optical functions, III-V semiconductors with a direct bandgap need to be integrated on top of the passive SOI waveguide circuits. We focus in this paper on the integration of InP/InGaAsP heterostructures emitting at 1.55 m on top of silicon-on-insulator waveguide circuits by means of a die to wafer bonding process, as shown in Fig. 1. Unprocessed InP/InGaAsP dies are bonded with its epitaxial layers down onto a processed SOI waveguide wafer, after which the InP substrate is removed. After substrate removal, the optoelectronic components can be fabricated in the bonded epitaxial layer.Integration of two different material systems by means of a wafer bonding process can be done either using direct molecular bonding or adhesive bonding. Direct molecular bonding 2 relies on the van der Waals interaction between both surfaces. As this is a short-range force, sub-nm rms roughness of the surfaces is required.3 Although this is obtainable on unprocessed SOI wafers using chemicalmechanical polishing ͑CMP͒-and is the preferred way to fabricate SOI layer stacks-it is more difficult to obtain on the processed SOI waveguide circuits and on epitaxially grown InP/InGaAsP substrates. Therefore, in this work adhesive bonding was chosen to bond the III-V epi-structures on top of SOI waveguide circuits. One of the main advantages of adhesive bonding is that the surface quality that is required for bonding is less stringent as the polymer wets the surface and fills the troughs of the surface. It is also tolerant to particle contamination to some extent, and the topography of the surfaces to be bonded can be ...

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