In scaled technologies, large cell-to-cell interference and F-N tunneling disturbance degrade threshold voltage (V t ) window which we can place program states. Moreover, in Triple Layer Cell (TLC) NAND Flash we should place seven program states (P 1~P7 ) in the narrow V t window, incurring large biterror rate (BER). In this paper, we propose a state re-ordering technique to increase the efficiency of V t window utilization in TLC NAND Flash memories. Our simulation results show that under equivalent V t window sizes, the proposed technique provides 12.5~18.4% smaller BER compared to conventional Gray-code mapping.
The voltage-frequency island (VFI) design paradigm has strong potential for achieving high energy efficiency in emerging communication centric many-core system-on-chip (SoC) technology called network-on-chip (NoC). In VFI design, each core is allocated into a suitable domain with different voltage and frequency considering the required workload. Most VFI NoC studies have focused on regular topologies. However, today's diversified applications demand custom NoC topologies to accommodate heterogeneous many-core architectures. In this paper, we propose a low-power custom topology generation method for constructing VFI NoCs, which embraces irregular topologies. The main objective of this work is to minimize energy consumption and communication resources, hence improving communication efficiency.
Additional gating elements are inserted at the outputs of scan flip-flop to freeze unnecessary transitions from scan flip-flops to combinational logic such that the hot temperature is avoided during scan shift. This paper presents a new physical-aware gating element insertion method performed after initial cell placement while satisfying timing and placement density constraints, thus it avoids hotspots during scan shift operation.
Three-dimensional integration technology results in area savings, platform power savings, and an increase in performance. Through-silicon via (TSV) assembly and manufacturing processes can potentially introduce defects. This may result in increases in manufacturing and test costs and will cause a yield problem. To improve the yield, spare TSVs can be included to repair defective TSVs. This paper proposes a new built-in self-test feature to identify defective TSV channels. For defective TSVs, this paper also introduces dynamic self-repair architectures using code-based and hardware-mapping based repair.Keywords: Through-silicon via, built-in self test, dynamic self repair, code-based repair, hardware mapping based repair.
8T SRAM have been considered for robust subthreshold SRAM design. Their subthreshold operation was successfully demonstrated through real silicon measurements. However, Monte-Carlo simulation results show that this SRAM still may not deliver sufficient reliability in subthreshold operation. In this work, we overcome this problem by properly sizing SRAM transistors. We utilize short-channel V t roll-off and inverse narrow-width effect for the sizing. Since minimum geometry transistors are employed in the SRAM bit-cell, these effects can have profound impact on SRAM stability. Hence, the proposed approach provides an efficient way to increase the yield of the 8T subthreshold SRAMs.
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