Dynamic Self-Repair Architectures for Defective Through-silicon Vias

Yang, Joon Sung; Han, Tae Hee; Kobla, Darshan; Ju, Edward L.

doi:10.4218/etrij.14.0113.0578

Cited by 2 publications

(1 citation statement)

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“…For TSV repair, most of the existing works require hardware redundancy architectures to enhance the yield of 3-D ICs [14]- [19], [21]. In these approaches, spare TSVs are included along with the signal TSVs and the faulty TSVs can be replaced with the spare ones to improve the overall yield during testing.…”

Section: Previous Workmentioning

confidence: 99%

Virtualization-Based Efficient TSV Repair for 3-D Integrated Circuits

et al. 2020

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Three-dimensional (3-D) integration offers a promising solution to the technology scaling barriers. Reliability of the 3-D Integrated Circuits (ICs) is highly dependent on the integrity of the underlying interconnect. Through Silicon Via (TSV) based 3-D ICs would suffer from low yield due to the faults in TSVs. In addition, TSVs introduce stress and noise in the substrate. Adding redundant TSVs for repairing the faulty ones has commonly been proposed to improve the yield of TSV-based 3-D ICs. The existing TSV repair approaches employ a number of spare TSVs in a group of signal TSVs. We propose a TSV virtualization based repair architecture which utilizes a single redundant TSV to repair multiple faulty TSVs. The proposed architecture relies on transmitting multiple bits through a single TSV using multi-level voltage quantization. It makes efficient use of the TSV redundancies in repairing the faulty TSVs. With less number of spare TSVs, the proposed architecture can reduce the area overhead by more than 70%. Reduction in the TSV count allows greater interconnect density and helps to mitigate the TSV-induced noise and stresses. Alternatively, for a similar number of spare TSVs, the proposed method can enhance the fault tolerance capability of the conventional approaches thus leading to an enhanced chip yield. The eye diagram simulations using an electrical model of the TSV show a reduction of less than 5% in noise margin when using a 16-level voltage quantization at a data rate of 5 Gbps which is typical for 3-D integration applications. INDEX TERMS 3-D integrated circuit, eye diagram simulations, multiple bits transmission, through silicon via (TSV), TSV Virtualization, TSV repair.

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Section: Previous Workmentioning

confidence: 99%