Physical-aware gating element insertion for thermal-safe scan shift operation

Abstract

Additional gating elements are inserted at the outputs of scan flip-flop to freeze unnecessary transitions from scan flip-flops to combinational logic such that the hot temperature is avoided during scan shift. This paper presents a new physical-aware gating element insertion method performed after initial cell placement while satisfying timing and placement density constraints, thus it avoids hotspots during scan shift operation.

A novel X-filling method for capture power reduction

“…The effect of IR drops is particularly problematic at near-threshold voltage condition which decreases the supply voltage to about the threshold voltage for the sake of energy efficiency. Test operations consume more power than normal operations because test patterns make large transitions in circuits under testing [1,2,3]. Timing failures that don't occur in normal operations can be generated by these test operations and these make the overkill problem [4,5].…”