Rapid atomic layer deposition (RALD) of SiO₂ thin films was achieved using trimethyl-aluminum and tris(tert-pentoxy)silanol (TPS) as the catalyst and Si precursor, respectively. A maximum growth rate as high as ∼28 nm/cycle was obtained by optimizing the catalyst layer density, whereas the previous reports showed lower values of 12 to 17 nm/cycle [Hausmann et al. Science2002, 298, 402-406; Burton et al. Chem. Mater. 2008, 20, 7031-7043]. When the growth temperature was increased from 140 to 230 °C, the growth rate was not much reduced and the TPS pulse time showing a saturated growth rate became rather longer. Si-CH₃, Si-OH, and Si-H bonds were not detected in infrared spectra from the RALD SiO₂ film grown at 230 °C. The film quality could be enhanced substantially by applying a higher growth temperature and an in situ post plasma treatment process.

The high interfacial trap density in GaAs MOS capacitors is one of the critical issues for realizing high mobility field-effect transistors. This paper proposes a new approach involving the high pressure thermal oxidation (HPO) of GaAs and subsequent HF etching prior to the deposition of an Al2O3 dielectric film. The HPO-treated MOS capacitors exhibited better electrical properties, such as reduced hysteresis and frequency dispersion compared to those of the control capacitors. These improvements were attributed to their reduced interfacial trap density. The relevant rationale is discussed based on the suppression of the Ga2O3 layer between the Al2O3 dielectric and GaAs semiconductor, which resulted from the As excess and Ga deficient surface modification via HPO and subsequent HF etching.

The electrical properties of La-silicate films grown by atomic layer deposition (ALD) on Ge substrates with different film configurations, such as various Si concentrations, Al2O3 interfacial passivation layers, and SiO2 capping layers, were examined. La-silicate thin films were deposited using alternating injections of the La[N{Si(CH3)3}2]3 precursor with O3 as the La and O precursors, respectively, at a substrate temperature of 310 °C. The Si concentration in the La-silicate films was further controlled by adding ALD cycles of SiO2. For comparison, La2O3 films were also grown using [La((i)PrCp)3] and O3 as the La precursor and oxygen source, respectively, at the identical substrate temperature. The capacitance-voltage (C-V) hysteresis decreased with an increasing Si concentration in the La-silicate films, although the films showed a slight increase in the capacitance equivalent oxide thickness. The adoption of Al2O3 at the interface as a passivation layer resulted in lower C-V hysteresis and a low leakage current density. The C-V hysteresis voltages of the La-silicate films with Al2O3 passivation and SiO2 capping layers was significantly decreased to ∼0.1 V, whereas the single layer La-silicate film showed a hysteresis voltage as large as ∼1.0 V.

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In the supramolecule area, the fabrication of a new concept called polyrotaxanes or poly-pseudo-rotaxanes remains challenging. We herein report the formation of a poly-pseudo-rotaxane in which the same salt-type guest serves both linking and threading in the resulting structure. The combination of A1/A2-thiopyridyl pillar[5]arene (L) and silver(I) trifluoroacetate in CHCl 3 /CH 3 OH afforded a one-dimensional (1D) poly-pseudo-rotaxane. In this structure, to our surprise, the AgCF 3 CO 2 guest not only links the di-armed L ligands via an infinite −L−Ag−L−Ag− arrangement but also threads into a pillar[5]arene cavity in a dimer form, (AgCF 3 CO 2 ) 2 . In contrast, the same reaction in CH 2 Cl 2 /CH 3 OH yielded a simple 1D coordination polymer because an included CH 2 Cl 2 molecule in the pillar[5]arene cavity prevents the threading of the silver(I) trifluoroacetate guest. Comparative 1 Hand 19 F-NMR studies support the solvent-dependent poly-pseudo-rotaxane formation at a lower concentration of L.

Nitric oxide (NO) post-oxidation annealing (POA) is an effective method for lowering the carbon component at an oxide/4H-SiC interface. However, this method has a drawback of additional oxidation by oxygen source from the NO gas. Atomic-layer-deposited (ALD) oxides subjected to ammonia (NH 3) annealing were employed to realize nitridation without oxidation process. Because NH 3annealed oxides have a drawback of high leakage current, deposition of dielectrics on ALD SiO 2 with subsequent NH 3 annealing were performed to reduce leakage current and to prevent oxidation, respectively. The employments of this process reduced interface trap density and surface roughness effectively while maintaining low leakage current.

Although GaAs is one of the most attractive channel materials for achieving high electron mobility, reduction of the interface state is still required for high quality MOS devices. In this paper, thermal oxidation under two pressures and various temperatures, and subsequent HF etching were performed to deactivate the interfacial states of the Al 2 O 3 /GaAs stack. High pressure oxidation (HPO) at 10 atm and 400 8C resulted in substantial improvement in the C-V frequency dispersion characteristics whereas the deactivation effect of the interfacial trap density under the thermal oxidations at 1 atm was not observed irrespective of the thermal oxidation temperature, ranging from 400 to 550 8C. Strong disparity between pressure and temperature was elucidated based on the existence of an efficient As excess layer and the prevention of unwanted Ga oxidation.

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