In this paper we present a simulation study of wafer fab ramp-up scenarios with the simulation software AutoSched AP. A generic factory model (MIMAC 1 from Int. SEMATECH) was adapted to simulate fab ramp-up scenarios. The model was customized to consider time phased modeling capability and time phased reporting. Additionally, an evaluation approach for the comparison of different ramp-up scenarios is presented. This approach helps to evaluate the ramp-up performance with different input parameters. A systematic variation of dispatch rules and lot sizes during ramp-up is shown
This paper gives an overview of advanced scheduling and dispatching policies for WIP (work in process) management within the wafer fabrication process. Additionally, the pros and cons of general WIP control philosophies are opposed. Several control policies are evaluated for the application in complex make-to-order environment such as ASIC production. Based on the real shop floor environment of Philips SMST and the currently used control policies a proposal is presented answering the following two questions:What are the requirements of tomorrow's WIP control systems applied in make-to-order wafer fabrication? How can these control policies be implemented and introduced on the shop floor using existing WIP control and scheduling systems?
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