We present an interface synthesis tool (design compiler) which can generate interface circuits automatically to expedite the IP (silicon intellectual property) integration process in SoC designs. The protocol specification issue is first addressed and a programming paradigm in SystemC language is developed. The methodology for interface synthesis is next elaborated. Conventional compiler techniques such as lexical analysis, syntax parsing and code generation are applied plus the new processing specific to interface synthesis. This includes protocol signal mapping proxy for additional semantic information, interface FSM synthesis for the controller of protocol conversion and architecture template mapping for the underlined hardware. Various interface design examples are conducted and the experimental results show the competitiveness of the proposed synthesis tool.
In this paper, we present an EDA tool for automatic generation of parallel CRC and parallel scrambler designs subject to different generator polynomials and parallel processing rates. The base architecture is derived from a state space transform scheme with fully pipelined pre-and post-processing blocks and the critical path is limited to 1 XOR delay only. The maximum input data width for CRC and scrambler designs are 64 and 32, respectively. It can also support the processing of data sequence length not an integral multiple of the parallel input width. Synthesis results indicate that for parallel CRC designs the maximum working frequency under UMC .18pm process is 265.6MHz and the maximum data rate is 17Gbps. For parallel scrambler designs, the corresponding numbers are 375Mhz and 12Gbps.
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