In an interweave cognitive radio system, cooperative spectrum sensing has been recognised as a key technology to enable secondary users to opportunistically access licensed spectrum band without harmful interference to primary users. At the same time, the unmanned aerial vehicle equipped with spectrum sensing and data transmission facilities is gaining more popularity in different applications. An unmanned aerial vehicle-based interweave cognitive radio is investigated in which the unmanned aerial vehicle is used as a secondary user, but unlike the participation of multiple secondary users in traditional cooperative spectrum sensing, a virtual cooperative spectrum sensing model is introduced into the periodic spectrum sensing frame structure. Afterwards, the authors further propose an energy-efficient virtual cooperative spectrum sensing with the sequential 0/1 fusion rule to reduce the average number of decisions without any loss in the detection performance. Sequentially, the authors formulate the optimisation of virtual cooperative spectrum sensing for unmanned aerial vehicle-based interweave cognitive ratio system as the optimal sequential 0/1 fusion problem on the basis of the K-out-of-N fusion rule and prove the formulated problem indeed has one optimal K, which yields the highest throughput. Finally, numerical simulations are presented to demonstrate the correctness of theoretical analyses and the effectiveness of the virtual cooperative spectrum sensing with the sequential 0/1 fusion rule.This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.
Charge‐pump phase‐locked loop (CP‐PLL) is widely used to generate timing signals in systems on chips (SoCs). However, the number of cores embedded in SoCs, the limited I/O port resources and the cost of external test equipment lead to the increase of test complexity and cost. An all‐digital built‐in self‐test structure of CP‐PLL especially suitable for low‐cost production tests when I/O port resources are limited is proposed. The structure is simple and easily implemented with just a few DFFs, MUXs and some existing circuits in CP‐PLL under test. It reduces the requirement of additional external test clocks and high‐performance test equipment, which decreases the test cost of the whole integrated circuits. Combined with the proposed calibration technique, it eliminates the effect of uncertain initial value of voltage controlled oscillator input voltage on the fault coverage. Thus, the reliability of test results is also increased. Experiment results demonstrate the effectiveness of the proposed scheme with high fault coverage of 99.16%. In addition, the physical chip design is presented to show low area overhead of 1.37%.
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