In an interweave cognitive radio system, cooperative spectrum sensing has been recognised as a key technology to enable secondary users to opportunistically access licensed spectrum band without harmful interference to primary users. At the same time, the unmanned aerial vehicle equipped with spectrum sensing and data transmission facilities is gaining more popularity in different applications. An unmanned aerial vehicle-based interweave cognitive radio is investigated in which the unmanned aerial vehicle is used as a secondary user, but unlike the participation of multiple secondary users in traditional cooperative spectrum sensing, a virtual cooperative spectrum sensing model is introduced into the periodic spectrum sensing frame structure. Afterwards, the authors further propose an energy-efficient virtual cooperative spectrum sensing with the sequential 0/1 fusion rule to reduce the average number of decisions without any loss in the detection performance. Sequentially, the authors formulate the optimisation of virtual cooperative spectrum sensing for unmanned aerial vehicle-based interweave cognitive ratio system as the optimal sequential 0/1 fusion problem on the basis of the K-out-of-N fusion rule and prove the formulated problem indeed has one optimal K, which yields the highest throughput. Finally, numerical simulations are presented to demonstrate the correctness of theoretical analyses and the effectiveness of the virtual cooperative spectrum sensing with the sequential 0/1 fusion rule.This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.
To ensure qualification of charge-pump locked-loop (CP-PLL), a complete built-in self-test (BIST) scheme should provide functions of measurement of the clock jitter and detection of faults in CP-PLL. This paper proposes a low cost BIST structure providing both the faults detected and timing jitter measured. The structure based on the proposed time-to-digital converter (TDC), which has high resolution and most blocks of TDC are based on the existing blocks in CP-PLL, reduces the test cost and area overhead. The circuit has been designed and simulated in TSMC 0.13 µm CMOS process. The simulation results show that the resolution is about 0.9865 ps and the fault coverage is 98.33%.
A defect-oriented built-in self-test (BIST) structure of charge-pump phase-locked loop (CP-PLL) for high fault coverage and low area overhead test solution is proposed. It employs a new structure of phase/frequency detector, a D flip-flop and some existing blocks in the PLL as the input stimulus generator and fault feature extracted devices for testing evaluation. Thus, no extra test stimulus or high-performance measured instruments are required for test. The structure is easily implemented and has a little influence on the performance of CP-PLL. Fault simulation results indicate that the proposed BIST structure has high fault coverage (98.75%) and low area overhead (0.78%).
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