UV-ozone exposure directly on the dielectric surface to get an OTFT mobility as high as 6.50 cm2(V s)−1.

We performed a systematic study of the influence of environmental conditions on the electrical performance characteristics of solution-processed 2,7-dioctyl [1] benzothieno[3,2-b][1]-benzothiophene (C8-BTBT) thin-film transistors (TFTs). Four environmental exposure conditions were considered: high vacuum (HV), O 2 , N 2 , and air. The devices exposed to O 2 and N 2 for 2 h performed in a manner similar to that of the device kept in HV. However, the device exposed to air for 2 h exhibited significantly better electrical properties than its counterparts. The average and highest carrier mobility of the 70 air-exposed C8-BTBT TFTs were 4.82 and 8.07 cm 2 V -1 s -1 , respectively. This can be compared to 2.76 cm 2 V -1 s -1 and 4.70 cm 2 V -1 s -1 , respectively, for the 70 devices kept in HV. Furthermore, device air stability was investigated. The electrical performance of C8-BTBT TFTs degrades after long periods of air exposure. Our work improves knowledge of charge transport behavior and mechanisms in C8-BTBT OTFTs. It also provides ideas that may help to improve device electrical performance further.

A clear technical demonstration of the critical role of the blocking layers, which has never been addressed sufficiently in previous work.

In this work, nanocrystalline silicon (nc-Si) films were achieved by using normally processing method of amorphous silica thin film transistors (a-Si TFTs), plasma enhanced chemical vapor deposition (PECVD). The effects of PECVD process parameters on the crystallization rate of nanocrystalline silicon films were comprehensively studied and then an optimized nanocrystalline silicon film has been achieved with a crystallinity of 50.87%. The electrical properties and stability of nc-Si TFTs are further investigated and compared with a-Si TFTs. The ΔVth of the nc-Si TFTs are 0.14 V and -3.32 V under positive bias-temperature-illumination stress (60°C, 30 V, 6000 nit) and negative bias-temperature-illumination stress (60°C, -30 V, 6000 nit) after 1 hour, which are 1.96 V and -5.51 V for a-Si TFT, respectively. The result reveals better photo stability of nc-Si TFTs than a-Si TFTs which is attributed to fewer defect states in nanocrystalline silicon films.

We have fabricated high stability nanocrystalline silicon (NanoSi) on large glass substrate and investigated the effects of silane content ratio (SC), power, space and pressure on NanoSi thin‐film growth, deposition rate and its electrical characteristics on bottom‐gate back‐channel etch TFTs using 4 mask process. The single film results show that the key factors affecting the deposition rate are power and silane content and a suitable thickness is benifit for high mobility TFT manufacture. Multiple sets of data show that the main impact factor for electrical charecteristics of NanoSi TFTs is SC and pressure. Through the analysis of bias stress data, we can find that the electrical stability of NanoSi TFTs is better than that of a‐Si:H TFTs with lower Vth shift about 2.22 V of PBTIS and ‐1.29 V of NBTIS. It is because the defect state of NanoSi is produced by charge trapping and is negligible.