Due to the high throughput and high computing capability of convolutional neural networks (CNNs), researchers are paying increasing attention to the design of CNNs hardware accelerator architecture. Accordingly, in this paper, we propose a block parallel computing algorithm based on the matrix transformation computing algorithm (MTCA) to realize the convolution expansion and resolve the block problem of the intermediate matrix. It enables high parallel implementation on hardware. Moreover, we also provide a specific calculation method for the optimal partition of matrix multiplication to optimize performance. In our evaluation, our proposed method saves more than 60% of hardware storage space compared with the im2col(image to column) approach. More specifically, in the case of large-scale convolutions, it saves nearly 82% of storage space. Under the accelerator architecture framework designed in this paper, we realize the performance of 26.7GFLOPS-33.4GFLOPS (depending on convolution type) on FPGA(Field Programmable Gate Array) by reducing bandwidth and improving data reusability. It is 1.2×–4.0× faster than memory-efficient convolution (MEC) and im2col, respectively, and represents an effective solution for a large-scale convolution accelerator.
In order to reduce the computation in the H.264 encoder, a new method for the motion search based on the zero-block detection is proposed in this paper. According to the characteristics of the transform and motion search in H.264, the zero-block detection is performed in the process of the motion search for the inter-frame encoding by comparing the Sum of the Absolute Differences (SAD) to a value related with the Quantization Parameter (QP). The process of the motion search will stop when a zero-block is detected, and the transform and quantization of this zero-block will be skipped, which leads to save a lot of time for the H.264 encoder. Simulation results showed that in contrast with the Jh47.4 video encoder, the proposed method reduces the computations and code length ' without loss of the encoding picture quality, and it is very ef$cient in real time low bit rate video encoding.
Multi-core architectures are widely used to enhance the microprocessor performance within a limited increase in time-to-market and power consumption of the chips. Toward the application of high-density data signal processing, this paper presents a novel heterogeneous multi-core architecture digital signal processor (DSP), YHFT-QDSP, with one RISC CPU core and 4 VLIW DSP cores. By three kinds of interconnection, YHFT-QDSP provides high efficiency message communication for inner-chip RISC core and DSP cores, inner-chip and inter-chip DSP cores. A parallel programming platform is specifically developed for the heterogeneous multi-core architecture of YHFT-QDSP. This parallel programming environment provides a parallel support library and a friendly interface between high level application softwares and multicore DSP. The 130 nm CMOS custom chip design results in a high speed and moderate power design. The results of typical benchmarks show that the interconnection structure of YHFT-QDSP is much better than other related structures and achieves better speedup when using the interconnection facilities in combing methods. YHFT-QDSP has been signed off and manufactured presently. The future applications of the multi-core chip could be found in 3G wireless base station, high performance radar, industrial applications, and so on.
The reliability of memory is an important issue. The rapid development of transistor technology makes the memory more prone to soft errors. Several recent efforts have proposed various designs to avoid the corruption of stored data by using Error Correction Codes (ECC). However, these designs tend to focus on one indicator, which means they cannot balance the electrical timing, area and power consumption constraints with the increasing of the chip-scale and the operating frequency. In this paper, we propose a design named TECED: A Two-Dimensional Error-Correction Codes Based Energy-Efficiency SRAM Design. We achieve higher energy-efficiency and lower hardware cost by using a two-dimensional error correction codes, and evaluate the design by considering the overall system performance. Comparing with the traditional Hamming code, the evaluation shows that the TECED reduces most of fifty percent of the area overhead and twenty-eight point five percent power consumption of the memory at a specific storage capacity.
This paper explores a dynamic buffer allocation technique to guide a distributed synchronization architecture to support efficient synchronization on multi-core Network-on-Chips (NoCs). The synchronization architecture features two physical buffers to be able to concurrently queue and handle synchronization requests issued by the local processor and remote processors via the on-chip network. Using the dynamic buffer allocation technique, the two physical buffers are dynamically allocated to form multiple virtual buffers in order to improve buffers' utilization. Experiments are carried on to evaluate buffers' utilization.
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