Due to the high throughput and high computing capability of convolutional neural networks (CNNs), researchers are paying increasing attention to the design of CNNs hardware accelerator architecture. Accordingly, in this paper, we propose a block parallel computing algorithm based on the matrix transformation computing algorithm (MTCA) to realize the convolution expansion and resolve the block problem of the intermediate matrix. It enables high parallel implementation on hardware. Moreover, we also provide a specific calculation method for the optimal partition of matrix multiplication to optimize performance. In our evaluation, our proposed method saves more than 60% of hardware storage space compared with the im2col(image to column) approach. More specifically, in the case of large-scale convolutions, it saves nearly 82% of storage space. Under the accelerator architecture framework designed in this paper, we realize the performance of 26.7GFLOPS-33.4GFLOPS (depending on convolution type) on FPGA(Field Programmable Gate Array) by reducing bandwidth and improving data reusability. It is 1.2×–4.0× faster than memory-efficient convolution (MEC) and im2col, respectively, and represents an effective solution for a large-scale convolution accelerator.
The development of the sensor network technology is playing more and more important role in our daily life. However, sensor data from different sources is hard to work together for lack of semantic. This paper proposed a solution to transforming sensor data to RDF based on SSN ontology. We design a XML-based mapping language (named SASML) which is used to annotate sensors and sources. Then, an algorithm (named SDRM) is designed to transform sensor data to RDF conforming to SSN ontology, based on the predefined SASML mapping file. Further, we have developed a prototype to demonstrate the effectiveness of our method.
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