Supporting Efficient Synchronization in Multi-core NoCs Using Dynamic Buffer Allocation Technique

Chen, Xiaowen; Lu, Zhonghai; Jantsch, Axel; Chen, Shuming; Lu, Jianzhuang; Hu-cheng, WU

doi:10.1109/isvlsi.2010.16

Cited by 2 publications

(1 citation statement)

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“…It has since then been used for a range of different applications and in different ways, for instance for different synchronization techniques [5,7,9] and for run-time partitioning of private/shared memory [6]. In this section we review the basic architecture of the DME, its main functions and features.…”

Section: Dme-enhanced Multi-core Noc Platformmentioning

confidence: 99%

Memory Architecture and Management in an NoC Platform

Jantsch

Chen

Naeem

et al. 2011

Scalable Multi-Core Architectures

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The memory organization and the management of the memory space is a critical part of every NoC based platform design. We propose a Data Management Engine (DME), that is a block of programmable hardware and part of every processing element. It off-loads the processing element (CPU, DSP, etc.) by managing the memory space, memory access and the communication over the on-chip network. The DME's main functions are virtual address translation, private and shared memory management, cache coherence protocol, support for memory consistency models, synchronization and protection mechanisms for shared memory communication. The DME is fully programmable and configurable thus allowing for customized support for high level data management functions such as dynamic memory allocation and abstract data types. This chapter describes the main concepts, design and functionality of the DME and presents case studies illustrating its usage and performance.Key words: Network on Chip, SoC Architecture, Memory Organization On-Chip Memory OrganizationOn-chip Computation is moving away from a sequential to a parallel paradigm leading to dozens, hundreds, and soon even thousands of cores and computational units on a single die. These many core chips can be highly homogeneous or irregular and heterogeneous, depending on the application area and market segment. At the same time, the communication infrastructure is developing into a similarly parallel structure, which is often called a Network-on-Chip (NoC). Shared, serial buses are replaced by pipelined communication networks that allow hundreds or thousands of communications going on concurrently at any time.Only the third member of the trio computation, communication, storage, is lacking behind in this rapid transformation of sequential into massively parallel activity. Among the profound obstacles against making memory access as parallel as computation and communication, are the usage of shared memory for communication and temporary storage, and the large divide between on-chip and off-chip memory technology.In 1995 Wulf and McKee described in a remarkable, short article a trend that is since then known as the approach to the memory wall [32]. Based on the observation that processor speed grows by 80% every year but memory access time decreases only by 7% per year, they predict that, if no invention breaks this

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Section: Dme-enhanced Multi-core Noc Platformmentioning

confidence: 99%