We extended our previous GWAS for psoriasis with a a multistage replication study including 8,312 cases and 12,919 controls from China as well as 3,293 cases, 4,188 controls from Germany and the USA, and 254 nuclear families from the USA. We identified 6 new susceptibility loci associated to psoriasis in Chinese, containing candidate genes ERAP1, PTTG1, CSMD1, GJB2, SERPINB8, ZNF816A (PCombined<5×10−8) and replicated one locus 5q33.1 (TNIP1/ANXA6) previously reported (PCombined=3.8×10−21) in European studies. Two of these loci showed evidence for association evidence in the German study, at ZNF816A and GJB2 with P=3.6×10−3 and P=7.9×10−3, respectively. ERAP1 and ZNF816A were preferentially associated with Type I (early onset) psoriasis in Chinese Han population (test for heterogeneity P=6.5×10−3 and P=1.5×10−3, respectively). Comparisons with previous GWAS of psoriasis highlight the heterogeneity of disease susceptibility between Chinese and European populations. Our study identifies new genetic susceptibility factors and suggests new biological pathways in psoriasis.

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

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