Post cleaning experiments for front end of the line (FEOL) CMP with silica and ceria slurries are carried out on commercial polishers with 300 mm oxide, nitride, and integrated shallow trench isolation (STI) wafers. Considering the charge attraction or repulsion between particles and wafer surface, both acidic and basic clean chemicals are applied at different stages in the post CMP process sequence. Diluted hydrogen peroxide in a non-contact megasonic cleaner is used to remove ceria abrasive particles and polish residues with high efficiency. On-platen buff clean with or without pad conditioning can make an impact on the post CMP cleaning performance. Post CMP cleaning splits are executed in order to evaluate the effectiveness of each of the process steps and their roles in the overall cleaning performance. Silica-based slurries are usually adopted for bulk oxide polish while ceria-based slurries are more suited for the final "buff" polish where high selectivity is required. The ever stringent requirements for scratch reduction lead to the trend of adopting nano-sized (< 60 nm) abrasive particles in all types of CMP slurries. However, the higher surface charges per area of these nanoparticles and the resulting stronger adhesion force between them and wafer surface necessitates the modification of the chemistry and optimization of post CMP (pCMP) cleaning process to meet the low defect requirement.Between silica and ceria abrasive particles, the latter are heavier in weight and irregular in shape (as opposed to circular like silica), and hence may present more challenges for pCMP cleaning from weight and geometry point of view. However, atomic force microscope (AFM) measurement suggests that the adhesion force of irregular ceria is much lower than that of spherical silica on the surface of TEOS oxide, SiN x , and poly-Si in both acidic and basic pH regimes.1 Unlike silica, ceria exhibit redox reactions on SiO x surface, which should be taken into account when selecting the chemicals for pCMP cleaning. Meanwhile, besides silica and ceria abrasive particles, a robust FEOL pCMP clean process need to remove organic additives from slurry itself; by-products or polish residues (PR) such as SiO x , SiN x , and poly-Si from the wafer; and debris from CMP consumables such as pad (PU, polyurethane), carrier (stainless steel), retaining ring (e.g., polyether ether ketone, PEEK), and roller brush (polyvinyl alcohol, PVA).The selection of proper chemicals is often the first step toward pCMP cleaning. However, design of cleaning sequence, exploitation of the tool hardware, and optimization of process parameters are equally critical to achieve maximum cleaning efficiency.2 During the final ("buff") polish step, for example, the use of hard vs. soft pads, in-situ vs. ex-situ conditioning, and pad rinse with DIW vs. clean chemical can all modulate defect generation to various degrees, and hence affect the overall post cleaning performance. In the post CMP clean module, cleaning with or without mechanical contact, brush or "penci...

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In this study, the monodisperse abrasive deposition ͑MDAD͒ system was developed to investigate the polishing mechanism of ceria abrasives for the chemical mechanical planarization of a wafer. Using the MDAD system, groups of ceria particles with a specific size were collected from slurry with various particle size distributions, and each group was deposited on a blanket silicon wafer to study the size effect of the ceria particle on polishing results. The effects of the ceria particle size on surface roughness, contact area ratio, and subsurface damages on the surface and subsurface crystallographic structure were investigated using atomic force microscopy, transmission electron microscopy, and a surface inspection system. A similar set of experiments was performed with types of ceria abrasive particles with the same diameter but different morphologies to investigate the effect of the ceria abrasive geometry on polishing results. In addition, the effect of the ceria particle size on the pattern loading was investigated by polishing the shallow trench isolation and high aspect ratio patterned wafers.A chemical mechanical planarization ͑CMP͒ process is widely used for planarization and node separation of metal and dielectric films to realize a multilevel layer. 1,2 During the CMP process, a rotating wafer is pressed face down onto a rotating resilient polishing pad, where the polishing slurry containing abrasive particles and chemical reagents carries out the material removal and polishing of the wafer surface. 3 Recently, the semiconductor industry has tried to change the polishing medium from the conventional silica-based slurry to the ceria ͑CeO 2 ͒-based slurry. The ceria abrasives offer merits such as high removal rate and high selectivity with polymer additives and exhibit no slurry agglomeration with pad lifetime. 4,5 However, the high scratch level and pattern loading effect of ceria abrasives at the initial stage of CMP in device patterning have limited their use. 6 There is insufficient knowledge of the nature of the contact phenomena between the ceria abrasive and the polishing layer. Therefore, the nature of the polishing characteristics of the ceria abrasive with large particle size distributions needs to be understood in detail. 7 Many researchers have taken different approaches to understand the relationship between the CMP process performance and the size of silica ͑SiO 2 ͒ particles utilizing the concept of a two-body wear mechanism between the slurry abrasives and the wafer. Also, researchers showed that the material removal rate depends on the mean size of active silica abrasives, of which the larger abrasives yield a higher removal rate by a deeper indentation. [8][9][10][11][12][13] Some results also showed that the oversize particles of the silica abrasive were the source of microscratches. 14,15 To quantify the effect of the abrasive size, colloidal silica ͑SiO 2 ͒ of a uniform particle size distribution is typically used. 16 But there is only a limited amount of research related to the relat...

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Temperature control to stabilize the microscale contact surface between the pad and wafer, especially to prevent pad surface degradation, plays an important role in chemical mechanical polishing (CMP) processing of sub-50-nm devices. In this work, we investigated the phenomenon of pad surface hardening for various process temperatures and developed an effective method to minimize changes of the mechanical properties of the pad surface using diamond conditioner. The pad hardening characteristics were measured based on the force-distance (F-D) curve obtained by atomic force microscopy (AFM), and thermogravimetric analysis (TGA). F-D curve data showed that the increase of the elastic modulus with pad usage time at high process temperature was $1.5 times higher than at low process temperature. Also, TGA of a used polishing pad revealed a link between the endothermic peak intensity at 600°C and pad surface hardening. To prevent surface glazing or hardening throughout the lifetime of a pad at high process temperature, the optimum diamond size was investigated. Pad wear was investigated for various diamond conditioners with diamond grit size ranging from 100 lm to 270 lm. The results of pad surface analysis using scanning electron microscopy (SEM) and three-dimensional optical profiling showed that the 210 lm grit size was best for removing deformed layers, with the pad surface remaining consistent during the lifetime of the pad as verified by TGA and the F-D curve. The results of pad surface analysis are important for the design of conditioners that can produce pads with stable dynamic mechanical properties and prolonged lifetime at high process temperature.