A 7nm CMOS technology platform for mobile and high performance compute application

Narasimha, S.; Jagannathan, B.; Oginö, Kazuhíde; Jaeger, D.; Greene, B.; Sheraw, C.; Zhao, Kai; Haran, B.; Kwon, U.; Mahalingam, A. K. M.; Kannan, Balaji; Morganfeld, B.; Dechene, J.; Radens, C.; Tessier, A.; Hassan, Asif; Narisetty, H.; Ahsan, Ishtiaq; Aminpur, M.; An, Chong Koo; Aquilino, Michael; Arya, Ankur; Augur, Rod; Baliga, N.; Bhelkar, R.; Biery, G.; Blauberg, A.; Borjemscaia, N.; Bryant, A.; Cao, Linjun; Chauhan, Vikrant; Chen, M.; Cheng, Lili; Choo, Jae; Christiansen, C.; Chu, Tao; Cohen, Boaz; Coleman, Ryan; Conklin, David; Crown, Stephen; Silva, A. da; Dechene, Dan J.; Derderian, Garo; Deshpande, Sadanand V.; Dilliway, G.; Donegan, Keith; Eller, M.; Fan, Y.; Fang, Qiang; Gassaria, A.; Gauthier, Robert; Ghosh, Sudip; Gifford, G.; Gordon, T.; Gribelyuk, M.; Han, Geng; Han, Jian; Han, Kwang Hee; Hasan, Mohd.; Higman, J.M.; Holt, J.; Hu, Lin; Huang, Luis; Huang, Chih-Chieh; Hung, Tsung-Shuen; Jin, Yufeng; Johnson, J. B.; Johnson, Stephen C.; Joshi, Vivek; Joshi, Manoj; Justison, Patrick; Kalaga, S.; Kim, T.; Kim, W.; Krishnan, R.; Krishnan, Bharat; Anil, K.G.; Kumar, Manoj; Lee, J.; Lee, R.; Lemon, John; Liew, San Leong; Lindo, P.; Lingalugari, M.; Lipiński, M.; Liu, P.; Liu, J.; Lucarini, Stephen; Ma, Wei; Maciejewski, E.; Madisetti, Shailesh; Malinowski, Arkadiusz; Jl, Mehta; Meng, Chuizhou; Mitra, Subhasish; Montgomery, C.; Nayfeh, Hasan M.; Nigam, T.; Northrop, G. A.; Onishi, K.; Ordonio, Christopher; Özbek, Merve; Pal, Rohit; Parihar, Sanjay; Patterson, Oliver D.; Ramanathan, Eswar; Ramirez, I.; Ranjan, Rakesh; Sarad, J.; Sardesai, V.; Saudari, Sangameshwar Rao; Schiller, C.; Senapati, B.; Serrau, C.; Shah, N.A.; Shen, Tian; Sheng, H.; Shepard, J.; Shi, Yong; Silvestre, Mary Claire; Singh, D.; Song, Zhigang; Sporre, J.; Srinivasan, P.; Sun, Zhen‐Gang; Sutton, A.K.; Sweeney, R.; Tabakman, K.; Tan, Michael Loong Peng; Wang, X.; Woodard, Eric; Xu, Guangyu; Xu, Donglai; Xuan, Truong; Yan, Yingjie; Yang, Ji Chul; Yeap, Kong Boon; Yu, Meiqi; Zainuddin, Abu; Zeng, Jia; Zhang, K.; Zhao, Meixiong; Zhong, Y.; Carter, R.; Lin, Ching-Ho; Grunow, Stephan; Child, Craig; Lagus, Mark E.; Fox, Robert; Kaste, E.; Gomba, G.; Samavedam, Srikanth; Agnello, P.; Sohn, Dong Kyun

doi:10.1109/iedm.2017.8268476

Cited by 36 publications

(17 citation statements)

References 1 publication

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“…Overall verification of above physics-based models was shown in our previous work [19]- [20] by comparing with the measurement data of the in-house 5nm node SOI nanowire [21]. Furthermore, this validated TCAD framework can well reproduce the published data of the state-of-the-art 7-nm node FinFET [22] and fairly guarantee the accuracy of our SPICE model.…”

Section: Spice Model and Simulation Methodssupporting

confidence: 66%

Investigation of Negative DIBL Effect and Miller Effect for Negative Capacitance Nanowire Field-Effect-Transistors

Huang

Zhu

et al. 2020

IEEE J. Electron Devices Soc.

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In this study, the negative DIBL (N-DIBL), negative differential resistance (NDR), and Miller effect of a negative capacitance nanowire filed-effect-transistor (negative capacitance (NC) NWFET) were analyzed by employing the custom-built SPICE model. In the simulation, the minimum subthreshold swing (SS) reduced to 40 mV/decade with negligible hysteresis, and the on-current amplified by approximately three times. The N-DIBL effect was analyzed by building a model, and the results indicated that the N-DIBL is negatively correlated with the SS. Hence, it is indispensable to make trade-offs between the N-DIBL and SS in NC NWFET applications. Moreover, the Miller effect of a NCFET-based inverter was investigated for the first time. The Miller effect of the NC NWFET-based inverter was considerably improved owing to a high on-current and negative internal gate voltage (when external gate voltage is set to 0V), which is beneficial for high-speed circuit building based on NC NWFETs. The overshoot of the NC NWFET-based inverter is ~43.1% less than that of the NWFET-based inverter, and the propagation delay of the NC NWFET-based inverter is ~73.1% less than that of the NWFET-based inverter at ferroelectric thickness TFE=3nm.

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Section: Spice Model and Simulation Methodssupporting

confidence: 66%

Investigation of Negative DIBL Effect and Miller Effect for Negative Capacitance Nanowire Field-Effect-Transistors

Huang

Zhu

et al. 2020

IEEE J. Electron Devices Soc.

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“…1 shows the overall verification of above physics-based models by comparing with the measurement data of the in-house 5nm node SOI nanowire [19]. Furthermore, this validated TCAD framework can well reproduce the published data of the state-of-the-art 7-nm node FinFET [20] and fairly guarantee the accuracy of our general compact model and 7-nm node ESD power clamp proposed in this work. The impact of 3D nature of nanoscale FinFET on circuit performance is well captured spontaneously because all our TCAD simulations are based on 3D FinFETs.…”

Section: Device Performance Analysis With Tcadsupporting

confidence: 61%

A Novel General Compact Model Approach for 7-nm Technology Node Circuit Optimization From Device Perspective and Beyond

Huo

Huang

et al. 2020

IEEE J. Electron Devices Soc.

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This work presents a novel general compact model for 7-nm technology node devices like FinFETs as an extension of previous conventional compact model that based on some less accurate elements including one-dimensional Poisson equation for three-dimensional devices and analytical equations for short channel effects, quantum effects and other physical effects. The general compact model exhibits efficient extraction, high accuracy, strong scaling capability and excellent transfer capability. As a demo application, two key design knobs of FinFET and their multiple impacts on RC control electrostatic discharge (ESD) power clamp circuit are systematically evaluated with implementation of the newly proposed general compact model, accounting for device design, circuit performance optimization and variation control. The performance of ESD power clamp can be improved extremely. This framework is also suitable for path-finding researches on 5-nm node gate-all-around devices, like nanowire (NW) FETs, nanosheet (NSH) FETs and beyond.

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“…Consensus on the transistor device structure to be used in CMOS chips versus year of first shipment, according to the ITRS 2.0, 2015 edition [40], and by its successor, the IRDS [41] (yellow bars). The orange bars refer to the experimental results from [43] on the "7 nm" node FinFETs and to TCAD analysis [44].…”

Section: Figurementioning

confidence: 99%

Quantum engineering of transistors based on 2D materials heterostructures

et al. 2018

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Quantum engineering entails atom-by-atom design and fabrication of electronic devices. This innovative technology that unifies materials science and device engineering has been fostered by the recent progress in the fabrication of vertical and lateral heterostructures of two-dimensional materials and by the assessment of the technology potential via computational nanotechnology. But how close are we to the possibility of the practical realization of next-generation atomically thin transistors? In this Perspective, we analyse the outlook and the challenges of quantum-engineered transistors using heterostructures of two-dimensional materials against the benchmark of silicon technology and its foreseeable evolution in terms of potential performance and manufacturability. Transistors based on lateral heterostructures emerge as the most promising option from a performance point of view, even if heterostructure formation and control are in the initial technology development stage.

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A 7nm CMOS technology platform for mobile and high performance compute application

Cited by 36 publications

References 1 publication

Investigation of Negative DIBL Effect and Miller Effect for Negative Capacitance Nanowire Field-Effect-Transistors

Investigation of Negative DIBL Effect and Miller Effect for Negative Capacitance Nanowire Field-Effect-Transistors

A Novel General Compact Model Approach for 7-nm Technology Node Circuit Optimization From Device Perspective and Beyond

Quantum engineering of transistors based on 2D materials heterostructures

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