A detailed analysis on the Sawyer-Tower method used in the measurement of large-signal output capacitance (Co) of power transistors is presented, followed by important design recommendations to obtain accurate results. Key factors affecting the proper implementation of the technique, such as power amplifier characteristics, load slew-rate, reference capacitor (C ref) and reverse conduction of the device are addressed, with accompanying simulation and experimental results for Si, SiC and GaN devices. A thorough investigation on the selection of C ref is presented, with a new equation to correctly determine its value for a given voltage swing and output capacitance range of the Device Under Test (DUT). We report that the Sawyer-Tower circuit impose the DUT to enter steady-state reverse conduction under certain conditions, leading to charge-voltage (QV) hysteresis patterns unrelated to Co. Our analysis reveals that the origin of this phenomenon is related to DUT's leakage current, and that it could be minimized by proper selection of the excitation frequency. This work intends to provide an effective guide on designing and using the Sawyer-Tower circuit and to induce further scientific insight in characterizing Co.
Recent research has reported an undesirable OFFstate loss in high-frequency soft-switching power converters, such as resonant converters. This loss is attributed to a hysteresis loss related to the charging-discharging process of the output capacitance of the power transistor. However, precise estimation of transistor power loss and its breakdown into ON-state and OFF-state losses is challenging in the MHz-range operation due to the small circuit size, parasitic effects, and limited accuracy in existing methods to measure low-loss systems. We present a measurement concept to perform a complete loss breakdown of MHz-range resonant converters, as well, directly determine the OFF-state losses in transistors, which is demonstrated for a GaNbased class-E inverter operating at 10 MHz. A novel and compact calorimeter was designed to measure the converter active-device losses down to 20 mW within a 5 % error. This measured loss is then separated into four components using a combination of average and instantaneous electrical measurements: transistor ON-state loss, transistor OFF-state loss, gate-driver internal loss and gate loss. A simple no-load technique was devised to evaluate the gate-driver internal loss. The proposed approach directly determines output-capacitance hysteresis losses during the actual converter operation, which is not possible with existing measurement methods. The presented knowledge of individual loss components permits better optimization of MHz-range power converters.
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