In this paper, methods for stacking ASML scribe lane alignment marks (SPM) and improving the mark performance at initial copper metal levels are discussed. The new mark designs and the theoretical reasons for mark design and/or integration change are presented. In previous joint publications between ASML and Freescale Semiconductor [1], improved overlay performance and alignment robustness for Back End Of Line (BEOL) layers by the application of stacked scribe lane marks (SPM) was presented.In this paper, further improvements are demonstrated through the use of optimized Versatile Scribe Lane Mark design (VSPM). With the application of stacked optimized VSPM-marks, the alignment signal strength of marks in the copper metal layer is increased compared to stacked SPM marks. The gains in signal strength stability, which is typical for stacked marks, as well as significantly reduced scribe lane usage, are also maintained. Through the placement of specially designed orthogonal scatter-bars in selected layers under the VSPM-marks, the alignment performance of initial inlaid metal layers is improved as well. The integration of these marks has been evaluated for the 90 nm and 65 nm technology nodes as part of a joint development program between the Crolles2 Alliance and ASML. A measured overlay improvement of ~10-15% was obtained by a strategy change from floating copper marks to stacked optimized VSPM marks.
Scatterometry mark design for improvement of the metrology performance is investigated in this joint work by ASML and STMicroelectronics. The studied marks are small, enabling metrology within the device area. The new mark-design approach reduces the effects from the mark-edges during the metrology measurement. For this, small assist-features are integrated in the mark design on the wafer. Thereby the new designs: 1. enlarge the metrology measurement-window, 2. optimize the repeatability and accuracy of the metrology at given mark size, 3. allow added functionality to existing marks within the current mark area, such as monitoring process asymmetry or multiple layer information, 4. allow for mark miniaturization at equal performance, enabling intra-field positioning. With this metrology tool-optical proximity correction (MT-OPC) included in the mark design, the metrology window is enhanced, while improved on-product overlay performance is obtained.
In the field of semiconductor manufacturing, the precise alignment of patterns on a wafer die is critical for the proper functioning of the resulting integrated circuit. However, various factors can cause deformation of the die, which can result in overlay errors and negatively impact device performance. In this work, we focused on the development of die nanotopography metrology, which is used to investigate the topography evolution of five selected dies over several process steps. The impact of manufacturing steps as film deposition, annealing and CMP on die shape deformation and its relation to different pattern densities is measured using optical interferometry. We show that full-die nano-topography measurements are able to detect stress-induced in-plane die distortions as an effect of different annealing processes on SOI or silicon-bulk substrates.
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