Study of µDBO overlay target size reduction for application broadening

Calado, V. E.; Depre, Jerome; Massacrier, Clément; Tarabrin, S. P.; Haren, Richard van; Dettoni, Florent; Bouyssou, R.; Dezauzier, C.

doi:10.1117/12.2297673

Cited by 6 publications

(5 citation statements)

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“…As the technology node continues to shrink, the DBO (diffraction-based overlay) strategy has showed impressive performance. Studies suggest that IBO is better for non-tool-induced shift, while DBO is better for tool-induced shift [158,159]. However, IBO has faced more contrasting challenges when SADP and SAQP patterning film stacks have been introduced, while DBO has shown less film stack dependence with good overlay precision [160].…”

Section: Overlay and Edge Placement Error (Epe) Challengesmentioning

confidence: 99%

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CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Radamson,

Miao,

Zhou

et al. 2024

Nanomaterials

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After more than five decades, Moore’s Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

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Section: Overlay and Edge Placement Error (Epe) Challengesmentioning

confidence: 99%

“…The uDBO metrology has also implemented muti-wavelength measurements. Compared with prior generations of dual-wavelength methodology, its accuracy and robustness to process variation have both been improved [159].…”

Section: Overlay and Edge Placement Error (Epe) Challengesmentioning

confidence: 99%

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Radamson,

Miao,

Zhou

et al. 2024

Nanomaterials

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“…Location C is measuring focus directly on the product without a target at all. However placing metrology targets in-die (B) is at the cost of valuable space [3]. Optical metrology targets are usually placed in the scribe area (A).…”

Section: Introductionmentioning

confidence: 99%

Focus sensing using placement and CD variation for high NA EUV lithography

Calado,

Mathijssen,

van Setten

et al. 2024

Optical and EUV Nanolithography XXXVII

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The small depth of focus of high-NA EUV systems asks for robust focus metrology and possibly even focus control. Fast optical focus metrology is possible with dedicated focus-sensitive targets that make use of mask-3D effects. It is beneficial to connect this optical focus measurement to the focus behavior of actual device structures. Focus errors of device structures can be determined by measuring Pattern Placement Errors (PPE) with e-beam since a focus error usually lead to a layout-dependent PPE. By using a large field of view SEM we can capture a large variety of pattern layouts in 1 image acquisition. This large pattern variety creates a lot of diversity resulting in a robust "on-device" focus measurement.

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“…In practice, scatterometry measurements were usually performed on unique periodic test structures situated on the scribe lines of the wafer. As the device scale continues to shrink, these metrology targets no longer provide a good correlation to the in-die structures [18][19][20][21]. More importantly, performing measurements on periodic structures instead of non-periodic structures could lead to additional measurement errors [22].…”

Section: Introductionmentioning

confidence: 99%

Non-integral model-based scatterometry for CD metrology of single high-aspect-ratio microstructures

Chein¹,

Yang²,

Fu³

et al. 2023

Surf. Topogr.: Metrol. Prop.

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This article presents an innovative model-based scatterometry method for CD metrology of single high-aspect-ratio (HAR) microstructures, which are increasingly utilized in advanced packaging, especially as vertical interconnects in three-dimensional integrated circuits. The rapidly growing aspect ratio of these HAR structures makes it challenging to monitor their critical dimensions (CD). Furthermore, conventional spectral reflectometry or scatterometry measurements on periodic metrology targets on the scribe lines of the wafer are inadequate in providing a reliable correlation with the in-die structures due to the integral nature of these measurements, which can result in additional measurement errors compared to measuring individual in-die structures. To address these challenges, we propose a novel scatterometry system that can achieve high-precision single-structure measurement of fine-pitch HAR structures with significantly improved light efficiency over conventional optical methods. Our system takes advantage of the high spatial coherence of the supercontinuum laser source and an optical NA-controlled design concept for precise light beam shaping, enabling high spatial resolution and superior light efficiency in measurements. Furthermore, we demonstrate a model-based measurement scheme that uses a virtual optical system for complete characterization of the sample profile. The experimental results show that the proposed system can accurately measure RDL structures with fine nominal spacing as small as 1 μm and an aspect ratio of 3:1 with high fidelity.

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Study of µDBO overlay target size reduction for application broadening

Cited by 6 publications

References 1 publication

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Focus sensing using placement and CD variation for high NA EUV lithography

Non-integral model-based scatterometry for CD metrology of single high-aspect-ratio microstructures

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