In this brief, two designs of low-error fixed-width signmagnitude parallel multipliers and two's-complement parallel multipliers for digital signal processing applications are presented. Given two n n nbit inputs, the fixed-width multipliers generate n n n-bit (instead of 2n n n-bit) products with low product error, but use only about half the area and less delay when compared with a standard parallel multiplier. In them, cost-effective carry-generating circuits are designed, respectively, to make the products generated more accurately and quickly. Applying the same approach, a low-error reduced-width multiplier with output bit-width between n and 2n has also been designed. Experimental results show that the proposed fixed-width and reduced-width multipliers have lower error than all other fixed-width multipliers and are still cost-effective. Due to these properties, they are very suitable for use in many multimedia and digital signal processing applications such as digital filtering, arithmetic coding, wavelet transformation, echo cancellation, etc.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.