Design of low-error fixed-width multipliers for DSP applications

Jou, Jer Min; Kuang, Shiann Rong; Chen, Ren Der

doi:10.1109/82.769795

Cited by 84 publications

(8 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In contrast, since our proposed Ax-BxP method minimizes the number of operand blocks used in computation, we achieve savings in terms of memory footprint and memory traffic in addition to computational energy savings. Other efforts, such as References [46][47][48][49][50][51] have taken a similar approach.…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Ax-BxP: Approximate Blocked Computation for Precision-reconfigurable Deep Neural Network Acceleration

Elangovan

Jain

Raghunathan

2022

ACM Trans. Des. Autom. Electron. Syst.

View full text Add to dashboard Cite

Precision scaling has emerged as a popular technique to optimize the compute and storage requirements of Deep Neural Networks (DNNs). Efforts toward creating ultra-low-precision (sub-8-bit) DNNs for efficient inference suggest that the minimum precision required to achieve a given network-level accuracy varies considerably across networks, and even across layers within a network. This translates to a need to support variable precision computation in DNN hardware. Previous proposals for precision-reconfigurable hardware, such as bit-serial architectures, incur high overheads, significantly diminishing the benefits of lower precision. We propose Ax-BxP, a method for approximate blocked computation wherein each multiply-accumulate operation is performed block-wise (a block is a group of bits), facilitating re-configurability at the granularity of blocks. Further, approximations are introduced by only performing a subset of the required block-wise computations to realize precision re-configurability with high efficiency. We design a DNN accelerator that embodies approximate blocked computation and propose a method to determine a suitable approximation configuration for any given DNN. For the AlexNet, ResNet50, and MobileNetV2 DNNs, Ax-BxP achieves improvement in system energy and performance, respectively, over an 8-bit fixed-point (FxP8) baseline, with minimal loss (<1% on average) in classification accuracy. Further, by varying the approximation configurations at a finer granularity across layers and data-structures within a DNN, we achieve improvement in system energy and performance, respectively.

show abstract

Section: Related Workmentioning

confidence: 99%

“…Operand bit-width truncation to minimize partial product generation is explored by References [46][47][48]. However, these efforts exhibit poor performance during small bit-width computations.…”

Section: Related Workmentioning

confidence: 99%

Ax-BxP: Approximate Blocked Computation for Precision-reconfigurable Deep Neural Network Acceleration

Elangovan

Jain

Raghunathan

2022

ACM Trans. Des. Autom. Electron. Syst.

View full text Add to dashboard Cite

show abstract

“…In contrast, since our proposed Ax-BxP method minimizes the number of operand blocks used in computation, we achieve savings in terms of memory footprint and memory traffic in addition to computational energy savings. Other efforts such as [42], [43], [44], [45], [46], [47] have taken a similar approach.…”

Section: Related Workmentioning

confidence: 99%

“…Operand bit-width truncation to minimize partial product generation is explored by efforts such as [42], [43] and [44]. However, these efforts exhibit poor performance during small bit-width computations.…”

Section: Related Workmentioning

confidence: 99%

Ax-BxP: Approximate Blocked Computation for Precision-Reconfigurable Deep Neural Network Acceleration

Elangovan¹,

Jain²,

Raghunathan³

2020

Preprint

View full text Add to dashboard Cite

Precision scaling has emerged as a popular technique to optimize the compute and storage requirements of Deep Neural Networks (DNNs). Efforts toward creating ultralow-precision (sub-8-bit) DNNs suggest that the minimum precision required to achieve a given network-level accuracy varies considerably across networks, and even across layers within a network, requiring support for variable precision in DNN hardware. Previous proposals such as bit-serial hardware incur high overheads, significantly diminishing the benefits of lower precision. To efficiently support precision re-configurability in DNN accelerators, we introduce an approximate computing method wherein DNN computations are performed block-wise (a block is a group of bits) and re-configurability is supported at the granularity of blocks. Results of block-wise computations are composed in an approximate manner to enable efficient re-configurability. We design a DNN accelerator that embodies approximate blocked computation and propose a method to determine a suitable approximation configuration for a given DNN. By varying the approximation configurations across DNNs, we achieve 1.11x-1.34x and 1.29x-1.6x improvement in system energy and performance respectively, over an 8-bit fixed-point (FxP8) baseline, with negligible loss in classification accuracy. Further, by varying the approximation configurations across layers and data-structures within DNNs, we achieve 1.14x-1.67x and 1.31x-1.93x improvement in system energy and performance respectively, with negligible accuracy loss.

show abstract

“…Many research efforts have been presented in literature to achieve hardware efficient implementation of a truncated multiplier. The basic idea of these techniques is to discard some of the less significant partial products and to introduce a compensation circuit that partly compensates for the dropped terms, thereby reducing approximation error (Jou et al, 1999;Van et al, 2000;Kidambi et al, 1996;Strollo et al, 2005;Lim, 1992;Kuang and Wang, 2006). Garofalo et al (2008) presented a truncated multiplier with minimum square error for every inputs' bit width.…”

Section: Introductionmentioning

confidence: 99%

Hardware Implementation of Truncated Multipliers Using Spartan-3AN, Virtex-4 and Virtex-5 FPGA Devices

Rais¹

2010

American Journal of Engineering and Applied Sciences

View full text Add to dashboard Cite

Problem statement: The development cost for Application Specific Integrated Circuits (ASICs) are high, algorithms should be verified and optimized before implementation. The Digital Signal Processing (DSP), image processing and multimedia requires extensive use of multiplication. The truncated multipliers can easily be implemented using Field Programmable Gate Array (FPGA) devices. Approach: This research presented the comparative study of Spartan-3AN, Virtex-4 and Virtex-5 FPGA devices. The implementation of standard and truncated multipliers is done using Very high speed integrated circuit Hardware Description Language (VHDL). Results: Remarkable reduction in FPGA resources, delay and power was achieved using truncated multipliers instead of standard parallel multipliers when the full precision of the standard multiplier is not required. The three devices showed significant improvement for truncated multipliers as compared to standard multipliers. Results showed that the anomaly in Spartan-3AN average connection and maximum pin delay have been efficiently reduced in Virtex-4 and Virtex-5 devices. Conclusion: The Virtex-5 FPGA device showed better performance as compared to Spartan-3AN and Virtex-4 FPGA devices

show abstract

Design of low-error fixed-width multipliers for DSP applications

Cited by 84 publications

References 5 publications

Ax-BxP: Approximate Blocked Computation for Precision-reconfigurable Deep Neural Network Acceleration

Ax-BxP: Approximate Blocked Computation for Precision-reconfigurable Deep Neural Network Acceleration

Ax-BxP: Approximate Blocked Computation for Precision-Reconfigurable Deep Neural Network Acceleration

Hardware Implementation of Truncated Multipliers Using Spartan-3AN, Virtex-4 and Virtex-5 FPGA Devices

Contact Info

Product

Resources

About