We present a wideband circularly polarized (CP) multiple-input multiple-output (MIMO) dielectric resonator antenna (DRA) with enhanced diversity. In the DRA element, two diagonal edges of the DR were truncated at 45 • to obtain a wider axial ratio larger than 0.65 GHz. The DRA element was excited by a cross-ring slot with specific slot-arm ratio through microstrip-line (MSTL) implemented at the backside of the FR4 substrate to generate CP fields. Small triangular stands at the edge of the DR were employed to hold it in place to avoid any degradation from the uncontrollable bonding agent used for attaching DR onto the FR4 substrate. The DRA achieved an impedance bandwidth better than 0.8 GHz with an antenna gain of 4.83 dBi. Using the DRA with the MSTL feed, two-element CP-DRA array was implemented with electromagnetic band-gap (EBG) structure etched onto the ground plane of the MSTL. The proposed architecture achieves isolation better than 26 dB over the desired frequency band without any performance degradation while maintaining its compact size in the array. Various diversity analysis was carried out on the implemented circularly polarized MIMO DRA. The measured results demonstrated that the proposed singly fed DRA with EBG on the ground plate is suitable for implementing wideband circular polarized MIMO antennas in a compact size.INDEX TERMS Dielectric resonator antennas, electromagnetic band-gap, MIMO, mutual coupling.

In this paper, we present a phased-array transceiver chip operating in full X-band (8-12 GHz) in 65-nm CMOS technology. The presented transceiver for the transmit/receive module (TRM) consists of a 6-bit passive phase shifter, a 6-bit attenuator, a bi-directional gain amplifier (BDGA), and a single pole double throw (SPDT) switch connected to the internal power amplifier (PA) and the low-noise amplifier (LNA) to serve as a duplexer. A 64-bit SPI scan-chain is integrated for digital TRM control. The transmitter achieves greater than 15 dB of power gain with 11.84 dBm at the output 1-dB compression point (OP1dB). To achieve a wideband operation of the passive phase shifter, we assigned two different resonant frequencies for the phase leading and lagging networks and aligned the slopes of their phase responses to have the desired phase shifts at the center frequency. The RMS phase error is less than 5 • , and the RMS amplitude error is less than 0.45 dB for all phase and attenuation states within 8-12 GHz while dissipating 216 mW dc power from a 1 V power supply. The receiver shows greater than 15 dB of power gain and has a noise figure (NF) of less than 8.4 dB for the entire X-band. The RMS phase error and the RMS amplitude error are less than 5 • and 0.45 dB, respectively, for all control states within 8-12 GHz. The receiver consumes 110 mW with a 1 V power supply. The transceiver chip occupies an area of 4 × 1.88 mm 2 .

This paper describes Monolithic Microwave Integrated Circuits (MMICs) for an X-band radar transceiver front-end implemented in 0.25 μm GaN High Electron Mobility Transistor (HEMT) technology. Two versions of single pole double throw (SPDT) T/R switches are introduced to realize a fully GaN-based transmit/receive module (TRM), each of which achieves an insertion loss of 1.21 dB and 0.66 dB at 9 GHz, IP1dB higher than 46.3 dBm and 44.7 dBm, respectively. Therefore, it can substitute a lossy circulator and limiter used for a conventional GaAs receiver. A driving amplifier (DA), a high-power amplifier (HPA), and a robust low-noise amplifier (LNA) are also designed and verified for a low-cost X-band transmit-receive module (TRM). For the transmitting path, the implemented DA achieves a saturated output power (Psat) of 38.0 dBm and output 1-dB compression (OP1dB) of 25.84 dBm. The HPA reaches a Psat of 43.0 dBm and power-added efficiency (PAE) of 35.6%. For the receiving path, the fabricated LNA measures a small-signal gain of 34.9 dB and a noise figure of 2.56 dB, and it can endure higher than 38 dBm input power in the measurement. The presented GaN MMICs can be useful in implementing a cost-effective TRM for Active Electronically Scanned Array (AESA) radar systems at X-band.

This paper presents a 280 GHz amplifier design strategy for a robust multistage amplifier in a sub-Terahertz (sub-THz) regime in 130 nm SiGe technology. The presented 280 GHz amplifier consists of 14 stages of the cascaded common emitter (CE) amplifier which offers a compact and improved-noise design due to the absence of the area-expensive and lossy baluns at such high frequencies. The interstage-matching network was flexibly constructed with two separate resonant tanks using metal–insulator–metal (MIM) capacitors and microstrip transmission lines (MSTLs) between each stage. The measured amplifier achieved a peak power gain of 10.9 dB at 283 GHz and a 3 dB gain of bandwidth of 30 GHz between 270 and 300 GHz. The peak output power of the amplifier was 0.8 dBm with an output of 1 dB gain compression point (OP1dB) of -3.6 dBm in simulation. The 14-stage amplifier consumes an area of 0.213 mm2, including all the pads. With the proposed interstage matching approach, a well-balanced 280 GHz amplifier has been demonstrated. The proposed design strategy is widely applicable to sub-THz receivers for future wireless communication systems.

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A W-band integer-N phase-locked loop (PLL) for a frequency hopping frequency modulation continuous wave (FMCW) radar is implemented in 65-nm CMOS technology. The cross-coupled voltage-controlled oscillator (VCO) was designed based on a systematic analysis of the VCO combined with its push-pull buffer to achieve high efficiency and high output power. To provide a frequency hopping functionality without any overhead in the implementation, the center frequency of the VCO is steeply controlled by the gate voltage of the buffer, which effectively modifies the susceptance of the VCO load. A stand-alone VCO with the proposed architecture is fabricated, and it achieves an output power of 13.5 dBm, a peak power efficiency of 9.6%, and a tuning range of 3.5%. The phase noise performance of the VCO is −92.6 dBc/Hz at 1-MHz and −106.1 dBc/Hz at 10 MHz offset. Consisting of a third-order loop filter and a divider chain with a total modulus of 48, the locking range of the implemented PLL with the cross-coupled VCO is recorded from 78.84 GHz to 84 GHz, and its phase noise is −85.2 dBc/Hz at 1-MHz offset.

In this paper, we present an 8-bit precision passive true-time delay (TTD) operating at 5-11 GHz in 65-nm CMOS technology. To achieve a precision time delay control, the 8-bit TTD employs a 4-bit time delay circuitry that utilizes two LC delay networks in parallel to reduce the effects of the nonideal lumped components and layout imbalance of a conventional TTD. To design an 8-bit TTD, a 4-bit TTD with conventional LC networks was also used for the 5 th bit to the 8 th bit (MSB) time-delay for coarse delay control. The implemented 8-bit TTD circuit achieved a minimum delay of 1.56 ps and a maximum delay of 400 ps, demonstrating the smallest loss per delay among the recently reported state-of-the-art silicon-based TTDs without dissipating any DC power and with a chip area of 2.76 ×1.01 mm 2 .INDEX TERMS CMOS, phased arrays, phase shifters, true-time delay.