No abstract

We propose an analytical model to reproduce the non-monotonic instability of the threshold voltage in 4H-SiC MOSFETs submitted to positive gate stress bias. Experimental analysis of the threshold voltage transients indicate that both electron and hole trapping take place in the gate dielectric or at the dielectric/semiconductor interface, responsible for a VTH increasing-decreasing-increasing pattern. At low/moderate stress fields (<7 MV/cm), the electron trapping kinetics responsible for positive VTH shift are modeled by a rate equation considering a trapping-inhibition model, that explains the logarithmic degradation kinetics. In the high field regime (>8 MV/cm), we propose that electrons can tunnel through the SiO2, be accelerated by the high field and generate holes through impact ionization (II) or anode hole injection (AHI). These holes are then trapped in the oxide, thus generating a negative VTH shift. This second process has an exponential time-dependency, as found through the analysis of the corresponding rate equations. The time constant of the positive VTH shift is evaluated as a function of stress voltage and temperature. The results indicate that the time constant is strongly dependent on the electric field (that accelerates electrons to generate holes), and not thermally activated, in agreement with theoretical considerations.

Similar charge to failure distributions with mean values of about 50 C/cm2 were measured for planar SiC MOSFETs and MOS capacitors. Fast occurring and saturating negative flatband and threshold voltage drops were found in time resolved 1 second long pulsed gate current stress with IG=1 mA/cm2 at T=150 °C. No substantial difference in VTH drift rate with VGS=28 V at T=150 °C was found after about 10 s recovery period for IG stressed devices compared with unstressed devices. Additionally, IG stressed and unstressed devices did not differ in final VTH shift at T=25 °C after VGS=28 V stress (during 3 hrs or 31 hrs). More gate oxide reliability characterization is important to determine if 1 mA/cm2 pulsed gate current stress creates any permanent changes to the SiC MOSFET device behaviour. Additionally, parametric shifts in VTH and RDSon was examined after long-term AC gate bias stress by a gate driver switching between-8V and 20V for four different commercially available SiC MOSFETs.