Non-monotonic threshold voltage variation in 4H-SiC metal–oxide–semiconductor field-effect transistor: Investigation and modeling

Abstract

We propose an analytical model to reproduce the non-monotonic instability of the threshold voltage in 4H-SiC MOSFETs submitted to positive gate stress bias. Experimental analysis of the threshold voltage transients indicate that both electron and hole trapping take place in the gate dielectric or at the dielectric/semiconductor interface, responsible for a VTH increasing-decreasing-increasing pattern. At low/moderate stress fields (<7 MV/cm), the electron trapping kinetics responsible for positive VTH shift are modeled by a rate equation considering a trapping-inhibition model, that explains the logarithmic degradation kinetics. In the high field regime (>8 MV/cm), we propose that electrons can tunnel through the SiO2, be accelerated by the high field and generate holes through impact ionization (II) or anode hole injection (AHI). These holes are then trapped in the oxide, thus generating a negative VTH shift. This second process has an exponential time-dependency, as found through the analysis of the corresponding rate equations. The time constant of the positive VTH shift is evaluated as a function of stress voltage and temperature. The results indicate that the time constant is strongly dependent on the electric field (that accelerates electrons to generate holes), and not thermally activated, in agreement with theoretical considerations.

Review and Outlook on GaN and SiC Power Devices: Industrial State-of-the-Art, Applications, and Perspectives

“…Other reports [29], [30], [31] show the presence of two phases in the dynamics of the shift, as shown in Fig. 9, which can be ascribed to the competition of two distinct trapping processes.…”

Transconductance Overshoot, a New Trap-Related Effect in AlGaN/GaN HEMTs

“…During the filling stress, a positive V TH shift is observed, with a logarithm dependence on the stress time. This behavior was previously detected in transistors based on silicon [30] Ga 2 O 3 [31], GaN [32], [33] and SiC [34], and is usually described by an "inhibition model" [30], [32] which assumes that when an electron is trapped, a Coulombic potential is generated, and this inhibits charge trapping in neighboring defects, thus decreasing the trapping rate. The long filling time explains why V TH positive shift and g m overshoot are not observed for short integration times (20 µs).…”

Correlating Interface and Border Traps With Distinctive Features of C–V Curves in Vertical Al2O3/GaN MOS Capacitors

“…Because these device technologies under development still suffer from significant trapping effects related to the MOS stack [16], [17], [18], control of the gate-stack quality is a critical issue that requires careful characterization during the process optimization loop. This calls for appropriate test structures and dependable experimental techniques for the characterization of the interface trap (IT) and border trap (BT) states, the latter being defects located in the oxide at 1-2 nm from the interface that can be easily reached by channel electrons through tunneling [16], [19], [20], [21], [22].…”