On the road to insertion of extreme ultraviolet (EUV) lithography into production at the 16 nm technology node and below, we are testing its integration into standard semiconductor process flows for 22 nm node devices.In this paper, we describe the patterning of two levels of a 22 nm node test chip using single-exposure EUV lithography; the other layers of the test chip were patterned using 193 nm immersion lithography. We designed a full-field EUV mask for contact and first interconnect levels using rule-based corrections to compensate for the EUV specific effects of mask shadowing and imaging system flare. The resulting mask and the 0.25-NA EUV scanner utilized for the EUV lithography steps were found to provide more than adequate patterning performance for the 22 nm node devices. The CD uniformity across the exposure field and through a lot of wafers was approximately 6.1% (3σ) and the measured overlay on a representative test chip wafer was 13.0 nm (x) and 12.2 nm (y). A trilayer resist process that provided ample process latitude and sufficient etch selectivity for pattern transfer was utilized to pattern the contact and first interconnect levels. The etch recipes provided good CD control, profiles and end-point discrimination.The patterned integration wafers have been processed through metal deposition and polish at the contact level and are now being patterned at the first interconnect level.
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A single precursor, octamethylcyclotetrasiloxane (OMCTS), was used to develop a pSiCOH interconnect dielectric with an ultralow dielectric constant k = 2.4. With no added porogen, the advanced pSiCOH dielectric has low pore size and low pore interconnectivity. The new OEx2.4 dielectric has a high carbon content with a significant fraction in the form of Si-CH2-Si bridging bond resulting in a film with relatively high modulus and increased resistance to process induced damage. The new OEx2.4 film shows significant improvement in device reliability (time dependent dielectric breakdown) over the reference k 2.55 and other k 2.4 dielectrics. This dielectric not only addresses the integration challenges but also provides capacitance benefit by retaining an overall lower integrated k value over the reference films. The results discussed in this paper indicate that the single-precursor OMCTS-based advanced pSiCOH, OEX2.4 dielectric is a strong candidate for sub-10 nm Cu/low k interconnects.
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A systematic approach was taken to identify methods to prevent post CMP corrosion of copper in 22nm interconnect structures. Line to line current leakage measurements (at various times post CMP) were used as a means to quantify the extent and time-dependence of copper corrosion. Interruption of the corrosion mechanism by the use of passivating agents in post-CMP clean chemistries is explored. A broad-based screening was conducted to identify aqueous formulations of passivating agents for protection of copper which do not have deleterious effects on line resistance and overall defectivity. A formulation was identified which was effective in preventing corrosion when applied during post CMP brush clean.
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