SRAM stability during word line disturb (access disturb) is becoming a key constraint for V,, scaling 111. Figure 1 illustrates the access disturb mechanism. In this paper we present a design methodology for $RAM stability during access disturb. In this methodology, the SRAM Access Disturb Margin (ADM) is defined as the ratio of the magnitude of the critical current to maintain SRAM stability ( I c~m ) to the sigma of ICKIT. Using ADM as a figure of merit, this methodology enables one to project the cell stability margin due to process variations, e.g. V, variation, during design of a SRAM cell. Using statistical analysis, the required stability margin for an application requirement such as array size and available redundancy can be estimated. Direct cell probing and m a y test can be used to verify that the stability target is met. SRAM Stability Margin Parameter Static [voltage] noise margin, as measured by the opening in the butterfly curve (Fig. 2) has often been used as a metric for SRAM stability [2]. Two drawbacks of the static noise margin are the inability to measure it with automatic inline testers and the inability to generate statistical information on SRAM fails. Alternatively, the SRAM "N-curve" [3] provides a way to satisfy both needs. Inline parametric testem can measure the voltage and the current on one intemal node of the same test structure used for the butterfly curve.Measured and simulated N-curves with both the word line and bit line held at VDU are shown in Figures 3 and 4. In Fig. 4, intercept I is determined by the SRAM pull down to transfer ritio (SRAM p ratio), while intercept 2 is related to the pull down to pull up relative strength (inverter p ratio). With the bit line held at VOO , if intercept I crosses intercept 2 when the word line tums on, the SRAM cell flips; mrtking the cell unstable during word line disturb. The delta between intercept 1 and 2 can thus be interpreted as thc static noise margin, or the critical voltage to maintain the SRAM stability (VCRIT). One can also characterize the cell stability by the peak current (IcRm). or the total area of the "barrier height" between intercept I and 2 in the unit of power (P,-R,T). As seen in Fig. 4, all three measures of stability are degraded when process variation is included in the simulation. We have confirmed by a Monte Carlo simulation that bits that fail due to VT variation have margin parameters equal to zero. Note that in Fig. 6 , I C~T has a relatively linear relationship with VT'S. To enable linear analysis and extrapolation, we chose ICm as the margin parameter.
SRAM Design for Stability MethodologyTo obtain the stability margin, we start with the canonical form:in which x, can be any parameter whose variation is of interest. In this work we focus on the VT variation as the first order effect (x,=V,,). We find that no specific VT correlation between transistors in an SRAM cell best describes the data, but one should note that some correlation could be expected depending on the cell layout details. The total...
