Energy consumption has become dominant issue for wireless internet of things (IoT) networks with battery-powered nodes. The prevailing mechanism allowing to reduce energy consumption is duty-cycling. In this technique the node sleeps most of the time and wakes up only at selected moments to extend the lifespan of nodes up to 5-10 years. Unfortunately, the scheduled duty-cycling technique is always a trade-off between energy consumption and delay in delivering data to the target node. The delay problem can be alleviated with an additional wake-up radio (WuR) channel. In the paper we present original power consumption models for various duty-cycling schemes. They are the basis for checking whether WuR approach is competitive with scheduled duty-cycling techniques. We determine the maximum energy level that an additional wake-up radio can consume to become a reasonable alternative of widely used duty-cycling techniques for typical IoT networks.
Abstract-The paper presents the extent of fault effects in FPGA based systems and concentrates on transient faults (induced by single event upsets -SEUs) within the configuration memory of FPGA. An original method of detailed analysis of fault effect propagation is presented. It is targeted at microprocessor based FPGA systems using the developed fault injection technique. The fault injection is performed at HDL description level of the microprocessor using special simulators and developed supplementary programs. The proposed methodology is illustrated for soft PicoBlaze microprocessor running 3 programs. The presented results reveal some problems with fault handling at the software level.
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