Tracing Fault Effects in FPGA Systems

Węgrzyn, Mariusz; Sosnowski, J.

doi:10.2478/eletel-2014-0012

Cited by 4 publications

(12 citation statements)

References 15 publications

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“…An example [16] of a modelled fault is shown in Figure 3. The HDL description of a LUT implementing a three-input OR gate is shown in Figure 3a.…”

Section: Faults Modellingmentioning

confidence: 99%

See 1 more Smart Citation

Optimal Reduction of Number of Test Vectors for Soft Processor Cores Implemented in FPGA

Węgrzyn¹,

Jamro²,

Dąbrowska-Boruch³

et al. 2021

Preprint

Self Cite

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This paper describes a new optimization methodology of testing vector sets reduction for testing of soft-processor cores and their individual blocks. The deterministic test vectors both for whole core and its individual blocks are investigated that significantly reduce the testing time and amount of test data that needs to be stored on the tester memory. The processor executes an assembler program which together with determined testing vectors ex-ercise its functionality. The new BIST methodology applicable at industrial testing of processor cores, diagnostics and dynamic reconfiguration of FPGA is proposed. This novel methodology combined with dynamic reconfiguration of FPGAs can be profitable applied for missions-critical i.e. FPGAs operate in space, or other difficult condition where are explore on radiation. Experimental results demonstrate that the proposed approach reduces many times testing time.

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“…An example [16] of a modelled fault is shown in Figure 3. The HDL description of a LUT implementing a three-input OR gate is shown in Figure 3a.…”

Section: Faults Modellingmentioning

confidence: 99%

“…The generation of the fault descriptions was implemented as a Perl script [11], [16]. All the instances of Look-Up-Tables LUTs contained in functional blocks of the processor are described in the VHDL code.…”

Section: Faults Modellingmentioning

confidence: 99%

Optimal Reduction of Number of Test Vectors for Soft Processor Cores Implemented in FPGA

Węgrzyn¹,

Jamro²,

Dąbrowska-Boruch³

et al. 2021

Preprint

Self Cite

View full text Add to dashboard Cite

show abstract

“…For transient faults Wegrzyn and Sosnowski investigated faults in the configuration memory. They tracked the fault in multilevel, and developed a fault injector simulator for this purpose [16] . Dumitriu et al developed a method that tolerates both transient and permanent faults using relocation.…”

Section: Related Workmentioning

confidence: 99%

“…Some of the researches used simple algorithm by considering the first fault as a transient fault, and the second consecutive to be permanent. Others used more sophisticated algorithms that measure the Mean Time Between Failures (MTBF) for every fault type and compare the MTBF for the occurred fault in the application to determine its type [12][13][14][15][16]. All the previous work use fixed data in their experiments and do not cope with the environmental changes.…”

Section: Introductionmentioning

confidence: 99%

Transient and Permanent Adaptive Fault Classifier for FPGA Applications in the Space

Tawfeek¹,

Alkabani²,

Egila³

et al. 2018

IJCDS

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Field Programmable Gate Array devices (FPGAs) are used in many applications. FPGAs are subjected to faults especially in the space where they are subjected to radiation. Faults in FPGAs may be recoverable (transient) or non-recoverable (permanent). Recoverable faults can be resolved by reconfiguring the system, on the other hand non-recoverable faults, require the relocation of the logic to a non-faulty area. This paper proposes an adaptive fault classifier that can be used to differentiate fault types. The classification guides the system to use the suitable recovery strategy. Experimental results show the operation of the classifier and adaptation layers, the proposed classifier layer is smaller in area compared to previous work. The adaptation layer works satisfactory to cope with environment changes. Both of the layers work independently of the design on any other layer.

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“…Models for Delay Change Due to Extra Stuck-at Parasitic Interconnect: Furthermore, another phenomenon observed in FPGA is caused by an extra parasitic interconnect that is stuck-at logic state '0' or '1' [23], [24]. This situation can occur when a logic node is tied to a specific logic value (by Fig.…”

Section: Circuit Level Configurations Inducing Odcs In Fpga Corementioning

confidence: 99%

Circuit Level Modeling of Extra Combinational Delays in SRAM-Based FPGAs Due to Transient Ionizing Radiation

Darvishi

Audet

Blaquiere

et al. 2014

IEEE Trans. Nucl. Sci.

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This paper presents circuit level models that explain the extra combinational delays in a SRAM-based FPGA (Virtex-5) due to Single Event Upsets (SEUs). Several scenarios of extra combinational delays are simulated based on the circuit architecture of the FPGA core, namely Configurable Logic Blocks (CLBs) and routing. It is found that the main delay contribution originates from extra interconnection lines that are unintentionally connected to the main circuit path via pass transistors activated by SEUs. Moreover, longer delay faults observed on Input/Ouput Blocks (IOBs) due to SEU were investigated through simulations. In all cases, results are in close agreement with the ones obtained experimentally while exposing the FPGA to proton irradiation. Index Terms-Configurable logic element, extra combinational delays, IBIS model, Input/Ouput Blocks (IOBs), observed delay change (ODC), single event upset (SEU), SRAM-based FPGA.

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Tracing Fault Effects in FPGA Systems

Cited by 4 publications

References 15 publications

Optimal Reduction of Number of Test Vectors for Soft Processor Cores Implemented in FPGA

Optimal Reduction of Number of Test Vectors for Soft Processor Cores Implemented in FPGA

Transient and Permanent Adaptive Fault Classifier for FPGA Applications in the Space

Circuit Level Modeling of Extra Combinational Delays in SRAM-Based FPGAs Due to Transient Ionizing Radiation

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