Circuit Level Modeling of Extra Combinational Delays in SRAM-Based FPGAs Due to Transient Ionizing Radiation

Abstract

This paper presents circuit level models that explain the extra combinational delays in a SRAM-based FPGA (Virtex-5) due to Single Event Upsets (SEUs). Several scenarios of extra combinational delays are simulated based on the circuit architecture of the FPGA core, namely Configurable Logic Blocks (CLBs) and routing. It is found that the main delay contribution originates from extra interconnection lines that are unintentionally connected to the main circuit path via pass transistors activated by SEUs. Moreover, longer delay faults observed on Input/Ouput Blocks (IOBs) due to SEU were investigated through simulations. In all cases, results are in close agreement with the ones obtained experimentally while exposing the FPGA to proton irradiation. Index Terms-Configurable logic element, extra combinational delays, IBIS model, Input/Ouput Blocks (IOBs), observed delay change (ODC), single event upset (SEU), SRAM-based FPGA.

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