The cache, a high-speed buffer establishing a storage hierarchy in the Model 85, is discussed in depth in this part, since it represents the basic organizational departure from other SYSTEM/360 computers.Discussed are organization and operation of the cache, including the mechanisms used to locate and retrieve data needed by the processor.The internal performance studies that led to use of the cache are described, and simulated performance of the chosen configuration is compared with that of a theoretical system having an entire SO-nanosecond main storage. Finally, the effects of varying cache parameters are discussed and tabulated.
The "high-end" water-cooled processors in the IBM Enterprise System/9000m product family use a CPU organization and cache structure which depart significantly from previous designs. The CPU organization includes multiple execution elements which execute Instructions out of sequence, and uses a new virtual register management algorithm to control them. It also contains a branch history table to remember recent branches and their target addresses so that instruction fetching and decoding can be directed more accurately. These models also use a two-level cache structure which provides a level 1 cache associated with each processor and a level 2 cache associated with central storage. The level 1 cache uses a store-through organization, and is split into two separate caches, one used for instruction fetching and the other for operand references. The level 2 cache uses a store-in method to handle stores.
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